+= read registers from userland

[raggedstone] / ethernet / source / top.vhd

diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd
index 34d0bdc6c558530e9aaa99e49ad046dbcdf63724..c031ae6f46540bd42c64d38f678e0f91e900030b 100644 (file)
--- a/ethernet/source/top.vhd
+++ b/ethernet/source/top.vhd
@@ -252,12 +252,14 @@ BLA2: FOR i in 3 downto 0 generate
 PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z';
 end generate;
 
 PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z';
 end generate;
 

-wb_adr_i <= wbm_adr_o (11 downto 2);
+wb_adr_i(11 downto 8) <= (others => '0');
+wb_adr_i(7 downto 2)  <= wbm_adr_o (7 downto 2);

 
 wb_clk_i <= PCI_CLOCK;
 
 
 wb_clk_i <= PCI_CLOCK;
 

-data(31 downto 0) <= wbm_adr_o;
-data(63 downto 32) <= (others => '0');
+data(31 downto 0)  <= wbm_adr_o;
+data(40 downto 33) <= wbm_adr_o (7 downto 0);
+data(63 downto 41) <= (others => '0');

 
 trig0(31 downto 0) <= (
        0 => wb_stb_i,
 
 trig0(31 downto 0) <= (
        0 => wb_stb_i,


@@ -345,7 +347,7 @@ Inst_eth_top: eth_top PORT MAP(
         wb_sel_i   => wb_sel_i  ,
         wb_we_i    => wb_we_i   ,
         wb_cyc_i   => wb_cyc_i  ,
         wb_sel_i   => wb_sel_i  ,
         wb_we_i    => wb_we_i   ,
         wb_cyc_i   => wb_cyc_i  ,

-        wb_stb_i   => wb_stb_i  ,
+        wb_stb_i   => wb_stb_i,

         wb_ack_o   => wb_ack_o  ,
         wb_err_o   => wb_err_o  ,
         m_wb_adr_o => m_wb_adr_o,
         wb_ack_o   => wb_ack_o  ,
         wb_err_o   => wb_err_o  ,
         m_wb_adr_o => m_wb_adr_o,