revert PCI_CLOCK in heartbeat project

[raggedstone] / dhwk / source / pci / comm_fsm.vhd

diff --git a/dhwk/source/pci/comm_fsm.vhd b/dhwk/source/pci/comm_fsm.vhd
index 82ecece801a6b2b304c7c24e07cec11d8428d31c..773512898f5e45cbf676db2a9334de7f1c25e1a3 100644 (file)
--- a/dhwk/source/pci/comm_fsm.vhd
+++ b/dhwk/source/pci/comm_fsm.vhd
@@ -63,7 +63,7 @@ begin
         if PCI_RSTn = '0' then
                 COMM_STATE <= "0000";
 
-        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+        elsif (rising_edge(PCI_CLOCK)) then
                 case COMM_STATE is
                 when ST_IDLE_COMM =>
                         if IO_READ = '1' then COMM_STATE <= ST_IO_READ;