white space; fixme

[raggedstone] / dhwk / source / pci / fifo_io_control.vhd

diff --git a/dhwk/source/pci/fifo_io_control.vhd b/dhwk/source/pci/fifo_io_control.vhd
index 03f914ac38a39f6d6ad6cdd6ab50b59d1f2d2e94..be853950ed3bf3940ade573b0aae29fae09dffcb 100644 (file)
--- a/dhwk/source/pci/fifo_io_control.vhd
+++ b/dhwk/source/pci/fifo_io_control.vhd
@@ -1,4 +1,4 @@
--- $Id: fifo_io_control.vhd,v 1.3 2007-03-11 12:24:35 sithglan Exp $
+-- $Id: fifo_io_control.vhd,v 1.4 2007-03-11 13:23:11 sithglan Exp $
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -35,7 +35,7 @@ begin
 
         process (PCI_CLOCK)
         begin
-                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if (rising_edge(PCI_CLOCK)) then
                         if (RESET = '1') then
                                 S_FIFO_WRITEn <= '1';
                                 SIG_S_ERROR <= '0';