bugfix

[raggedstone] / dhwk / fifo.xco

diff --git a/dhwk/fifo.xco b/dhwk/fifo.xco
index 8dde1a2a86fb7b1ed52627dcabb7f3fde6f8edb3..9b54e6720af7a31c55d05618a9cc29e86f0e3fc3 100644 (file)
--- a/dhwk/fifo.xco
+++ b/dhwk/fifo.xco
@@ -1,17 +1,3 @@
-##############################################################
-#
-# Xilinx Core Generator version J.30
-# Date: Sat Mar 10 21:20:43 2007
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#

 # BEGIN Project Options
 SET addpads = False
 SET asysymbol = False
 # BEGIN Project Options
 SET addpads = False
 SET asysymbol = False


@@ -37,7 +23,7 @@ SELECT Fifo_Generator family Xilinx,_Inc. 3.2
 # BEGIN Parameters
 CSET almost_empty_flag=true
 CSET almost_full_flag=true
 # BEGIN Parameters
 CSET almost_empty_flag=true
 CSET almost_full_flag=true

-CSET component_name=fifo_generator_v3_2
+CSET component_name=dhwk_fifo

 CSET data_count=false
 CSET data_count_width=12
 CSET dout_reset_value=0
 CSET data_count=false
 CSET data_count_width=12
 CSET dout_reset_value=0


@@ -72,5 +58,3 @@ CSET write_data_count=false
 CSET write_data_count_width=12
 # END Parameters
 GENERATE
 CSET write_data_count_width=12
 # END Parameters
 GENERATE

-# CRC: c795162c
-