signal SPC_RDY_OUT : std_logic;\r
signal watch : std_logic;\r
signal control0 : std_logic_vector(35 downto 0);\r
- signal data : std_logic_vector(63 downto 0);\r
- signal trig0 : std_logic_vector(7 downto 0);\r
+ signal data : std_logic_vector(95 downto 0);\r
+ signal trig0 : std_logic_vector(31 downto 0);\r
\r
component MESS_1_TB\r
Port ( DEVSELn : In std_logic;\r
(\r
control : in std_logic_vector(35 downto 0);\r
clk : in std_logic;\r
- data : in std_logic_vector(63 downto 0);\r
- trig0 : in std_logic_vector(7 downto 0)\r
+ data : in std_logic_vector(95 downto 0);\r
+ trig0 : in std_logic_vector(31 downto 0)\r
);\r
end component;\r
\r
LED_4 <= '0';\r
LED_5 <= not watch;\r
PCI_INTAn <= watch;\r
- trig0(7 downto 0) <= (others => '0');\r
- data(31 downto 0) <= PCI_AD(31 downto 0);\r
- data(32) <= watch;\r
+ trig0(31 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');\r
+ data(0) <= watch;\r
\r
- data(33) <= R_EFn;\r
- data(34) <= R_HFn;\r
- data(35) <= R_FFn;\r
- data(36) <= R_FIFO_READn;\r
- data(37) <= R_FIFO_RESETn;\r
- data(38) <= R_FIFO_RTn;\r
- data(39) <= R_FIFO_WRITEn;\r
- data(40) <= S_EFn;\r
- data(41) <= S_HFn;\r
- data(42) <= S_FFn;\r
- data(43) <= S_FIFO_READn;\r
- data(44) <= S_FIFO_RESETn;\r
- data(45) <= S_FIFO_RTn;\r
- data(46) <= S_FIFO_WRITEn;\r
- data(47) <= SERIAL_IN;\r
- data(48) <= SPC_RDY_IN;\r
- data(49) <= SERIAL_OUT;\r
- data(50) <= SPC_RDY_OUT;\r
+ data(1) <= R_EFn;\r
+ data(2) <= R_HFn;\r
+ data(3) <= R_FFn;\r
+ data(4) <= R_FIFO_READn;\r
+ data(5) <= R_FIFO_RESETn;\r
+ data(6) <= R_FIFO_RTn;\r
+ data(7) <= R_FIFO_WRITEn;\r
+ data(8) <= S_EFn;\r
+ data(9) <= S_HFn;\r
+ data(10) <= S_FFn;\r
+ data(11) <= S_FIFO_READn;\r
+ data(12) <= S_FIFO_RESETn;\r
+ data(13) <= S_FIFO_RTn;\r
+ data(14) <= S_FIFO_WRITEn;\r
+ data(15) <= SERIAL_IN;\r
+ data(16) <= SPC_RDY_IN;\r
+ data(17) <= SERIAL_OUT;\r
+ data(18) <= SPC_RDY_OUT;\r
+ data(26 downto 19) <= S_FIFO_Q_OUT;\r
+ data(34 downto 27) <= R_FIFO_Q_OUT;\r
+ data(66 downto 35) <= PCI_AD(31 downto 0);\r
+ data(70 downto 67) <= PCI_CBEn(3 downto 0);\r
\r
I19 : MESS_1_TB\r
Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r