- trig0(7 downto 0) <= (others => '0');\r
- data(31 downto 0) <= PCI_AD(31 downto 0);\r
- data(32) <= watch;\r
- \r
- data(33) <= R_EFn;\r
- data(34) <= R_HFn;\r
- data(35) <= R_FFn;\r
- data(36) <= R_FIFO_READn;\r
- data(37) <= R_FIFO_RESETn;\r
- data(38) <= R_FIFO_RTn;\r
- data(39) <= R_FIFO_WRITEn;\r
- data(40) <= S_EFn;\r
- data(41) <= S_HFn;\r
- data(42) <= S_FFn;\r
- data(43) <= S_FIFO_READn;\r
- data(44) <= S_FIFO_RESETn;\r
- data(45) <= S_FIFO_RTn;\r
- data(46) <= S_FIFO_WRITEn;\r
- data(47) <= SERIAL_IN;\r
- data(48) <= SPC_RDY_IN;\r
- data(49) <= SERIAL_OUT;\r
- data(50) <= SPC_RDY_OUT;\r
+ trig0(31 downto 0) <= (\r
+ 0 => watch,\r
+ 1 => R_FIFO_READn,\r
+ 2 => R_FIFO_WRITEn,\r
+ 3 => S_FIFO_READn,\r
+ 4 => S_FIFO_WRITEn, \r
+ 16 => PCI_AD(0),\r
+ 17 => PCI_AD(1),\r
+ 18 => PCI_AD(2),\r
+ 19 => PCI_AD(3),\r
+ 20 => PCI_AD(4),\r
+ 21 => PCI_AD(5),\r
+ 22 => PCI_AD(6),\r
+ 23 => PCI_AD(7),\r
+ 27 => PCI_FRAMEn,\r
+ 28 => PCI_CBEn(0),\r
+ 29 => PCI_CBEn(1),\r
+ 30 => PCI_CBEn(2),\r
+ 31 => PCI_CBEn(3),\r
+ others => '0');\r
+\r
+ data(0) <= watch;\r
+ data(1) <= R_EFn;\r
+ data(2) <= R_HFn;\r
+ data(3) <= R_FFn;\r
+ data(4) <= R_FIFO_READn;\r
+ data(5) <= R_FIFO_RESETn;\r
+ data(6) <= R_FIFO_RTn;\r
+ data(7) <= R_FIFO_WRITEn;\r
+ data(8) <= S_EFn;\r
+ data(9) <= S_HFn;\r
+ data(10) <= S_FFn;\r
+ data(11) <= S_FIFO_READn;\r
+ data(12) <= S_FIFO_RESETn;\r
+ data(13) <= S_FIFO_RTn;\r
+ data(14) <= S_FIFO_WRITEn;\r
+ data(15) <= SERIAL_IN;\r
+ data(16) <= SPC_RDY_IN;\r
+ data(17) <= SERIAL_OUT;\r
+ data(18) <= SPC_RDY_OUT;\r
+ data(26 downto 19) <= S_FIFO_Q_OUT;\r
+ data(34 downto 27) <= R_FIFO_Q_OUT;\r
+ data(66 downto 35) <= PCI_AD(31 downto 0);\r
+ data(70 downto 67) <= PCI_CBEn(3 downto 0);\r
+ data(71) <= PCI_FRAMEn;\r