WRITE_XX7_6 : Out std_logic );\r
end component;\r
\r
-component fifo_generator_v3_2\r
+component dhwk_fifo\r
port (\r
clk: IN std_logic;\r
din: IN std_logic_VECTOR(7 downto 0);\r
LED_4 <= '0';\r
LED_5 <= not watch;\r
PCI_INTAn <= watch;\r
- trig0(31 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');\r
+ trig0(31 downto 0) <= (\r
+ 0 => watch,\r
+ 1 => R_FIFO_READn,\r
+ 2 => R_FIFO_WRITEn,\r
+ 3 => S_FIFO_READn,\r
+ 4 => S_FIFO_WRITEn, \r
+ 16 => PCI_AD(0),\r
+ 17 => PCI_AD(1),\r
+ 18 => PCI_AD(2),\r
+ 19 => PCI_AD(3),\r
+ 20 => PCI_AD(4),\r
+ 21 => PCI_AD(5),\r
+ 22 => PCI_AD(6),\r
+ 23 => PCI_AD(7),\r
+ 27 => PCI_FRAMEn,\r
+ 28 => PCI_CBEn(0),\r
+ 29 => PCI_CBEn(1),\r
+ 30 => PCI_CBEn(2),\r
+ 31 => PCI_CBEn(3),\r
+ others => '0');\r
+\r
data(0) <= watch;\r
- \r
data(1) <= R_EFn;\r
data(2) <= R_HFn;\r
data(3) <= R_FFn;\r
data(26 downto 19) <= S_FIFO_Q_OUT;\r
data(34 downto 27) <= R_FIFO_Q_OUT;\r
data(66 downto 35) <= PCI_AD(31 downto 0);\r
+ data(70 downto 67) <= PCI_CBEn(3 downto 0);\r
+ data(71) <= PCI_FRAMEn;\r
\r
I19 : MESS_1_TB\r
Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
WRITE_XX7_6=>WRITE_XX7_6 );\r
\r
-receive_fifo : fifo_generator_v3_2\r
+receive_fifo : dhwk_fifo\r
port map (\r
clk => PCI_CLOCK,\r
din => R_FIFO_D_IN,\r
full => R_FFn,\r
prog_full => R_HFn);\r
\r
-send_fifo : fifo_generator_v3_2\r
+send_fifo : dhwk_fifo\r
port map (\r
clk => PCI_CLOCK,\r
din => S_FIFO_D_IN,\r