--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_WR_0.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity CONFIG_WR_0 is\r
- port\r
- (\r
- ADDR_REG :in std_logic_vector(31 downto 0);\r
- CF_WR_COM :in std_logic;\r
- IRDY_REGn :in std_logic;\r
- TRDYn :in std_logic;\r
- CONF_WR_04H :out std_logic; \r
- CONF_WR_10H :out std_logic; \r
- CONF_WR_3CH :out std_logic\r
---CONF_WR_40H :out std_logic \r
- );\r
-end entity CONFIG_WR_0;\r
-\r
-architecture CONFIG_WR_0_DESIGN of CONFIG_WR_0 is\r
-\r
---\r
---\r
---\r
---\r
---\r
--- PCI Configuration Space Header\r
---\r
--- \ Bit\r
--- \\r
---Address |31 24|23 16|15 8|7 0| \r
------------------------------------------------------------------\r
---00 |Device ID |Vendor ID | \r
---04 |Status |Command |\r
---08 |Class Code |Revision ID |\r
---0C |BIST |Header Type |Latency T. |Cache L.S. |\r
---10-24 |Base Address Register |\r
---28 |Cardbus CIS Pointer |\r
---2C |Subsystem ID |Subsystem Vendor ID |\r
---30 |Expansion ROM Base Address |\r
---34 |Reserved |\r
---38 |Reserved |\r
---3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line |\r
---40-FF | |\r
------------------------------------------------------------------\r
-\r
-\r
---PCI Bus Commands \r
---C/BE[3..0] Command Type\r
---------------------------------------\r
--- 0000 Interrupt Acknowledge\r
--- 0001 Special Cycle\r
--- 0010 I/O Read\r
--- 0011 I/O Write\r
--- 0100 Reserved\r
--- 0101 Reserved\r
--- 0110 Memory Read\r
--- 0111 Memory Write\r
---\r
--- 1000 Reserved\r
--- 1001 Reserved\r
--- 1010 Configuration Read\r
--- 1011 Configuration Write\r
--- 1100 Memory Read Multiple \r
--- 1101 Dual Address Cycle\r
--- 1110 Memory Read Line\r
--- 1111 Memory Write and Invalidate\r
-\r
-\r
---PCI Byte Enable \r
---C/BE[3..0] gueltige Datenbits \r
--------------------------------\r
--- 0000 AD 31..0\r
--- 1000 AD 23..0\r
--- 1100 AD 15..0\r
--- 1110 AD 7..0\r
-\r
- constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000";\r
- constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001";\r
- constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010";\r
- constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011";\r
- constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100";\r
- constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101";\r
- constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110";\r
- constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111";\r
- constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000";\r
- constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001";\r
- constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010";\r
- constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011";\r
- constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100";\r
- constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101";\r
- constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110";\r
- constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";\r
-\r
- signal CONFIG_ADDR :std_logic_vector(7 downto 0); \r
- signal CONFIG_WRITE :std_logic_vector(3 downto 0); \r
-\r
-\r
-begin\r
-\r
---*******************************************************************\r
---******************* PCI Write Configuration Address ***************\r
---*******************************************************************\r
-\r
- CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);\r
-\r
-\r
- process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR) \r
- begin\r
-\r
- if CF_WR_COM = '1' and IRDY_REGn = '0' and TRDYn = '0' then\r
-\r
- if CONFIG_ADDR = X"04" then\r
- CONFIG_WRITE <= "0001";\r
-\r
- elsif CONFIG_ADDR = X"10" then\r
- CONFIG_WRITE <= "0010";\r
-\r
- elsif CONFIG_ADDR = X"3C" then\r
- CONFIG_WRITE <= "0100";\r
-\r
--- elsif CONFIG_ADDR = X"40" then CONFIG_WRITE <= "1000";\r
- else\r
- CONFIG_WRITE <= "0000";\r
- end if;\r
- else \r
- CONFIG_WRITE <= "0000";\r
- end if;\r
- end process;\r
-\r
- CONF_WR_04H <= CONFIG_WRITE(0); \r
- CONF_WR_10H <= CONFIG_WRITE(1); \r
- CONF_WR_3CH <= CONFIG_WRITE(2); \r
---CONF_WR_40H <= CONFIG_WRITE(3); \r
-\r
-end architecture CONFIG_WR_0_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_WR_0.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_WR_0 is
+ port
+ (
+ ADDR_REG :in std_logic_vector(31 downto 0);
+ CF_WR_COM :in std_logic;
+ IRDY_REGn :in std_logic;
+ TRDYn :in std_logic;
+ CONF_WR_04H :out std_logic;
+ CONF_WR_10H :out std_logic;
+ CONF_WR_3CH :out std_logic
+--CONF_WR_40H :out std_logic
+ );
+end entity CONFIG_WR_0;
+
+architecture CONFIG_WR_0_DESIGN of CONFIG_WR_0 is
+
+--
+--
+--
+--
+--
+-- PCI Configuration Space Header
+--
+-- \ Bit
+-- \
+--Address |31 24|23 16|15 8|7 0|
+-----------------------------------------------------------------
+--00 |Device ID |Vendor ID |
+--04 |Status |Command |
+--08 |Class Code |Revision ID |
+--0C |BIST |Header Type |Latency T. |Cache L.S. |
+--10-24 |Base Address Register |
+--28 |Cardbus CIS Pointer |
+--2C |Subsystem ID |Subsystem Vendor ID |
+--30 |Expansion ROM Base Address |
+--34 |Reserved |
+--38 |Reserved |
+--3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line |
+--40-FF | |
+-----------------------------------------------------------------
+
+
+--PCI Bus Commands
+--C/BE[3..0] Command Type
+--------------------------------------
+-- 0000 Interrupt Acknowledge
+-- 0001 Special Cycle
+-- 0010 I/O Read
+-- 0011 I/O Write
+-- 0100 Reserved
+-- 0101 Reserved
+-- 0110 Memory Read
+-- 0111 Memory Write
+--
+-- 1000 Reserved
+-- 1001 Reserved
+-- 1010 Configuration Read
+-- 1011 Configuration Write
+-- 1100 Memory Read Multiple
+-- 1101 Dual Address Cycle
+-- 1110 Memory Read Line
+-- 1111 Memory Write and Invalidate
+
+
+--PCI Byte Enable
+--C/BE[3..0] gueltige Datenbits
+-------------------------------
+-- 0000 AD 31..0
+-- 1000 AD 23..0
+-- 1100 AD 15..0
+-- 1110 AD 7..0
+
+ constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000";
+ constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001";
+ constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010";
+ constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011";
+ constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100";
+ constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101";
+ constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110";
+ constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111";
+ constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000";
+ constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001";
+ constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010";
+ constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011";
+ constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100";
+ constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101";
+ constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110";
+ constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";
+
+ signal CONFIG_ADDR :std_logic_vector(7 downto 0);
+ signal CONFIG_WRITE :std_logic_vector(3 downto 0);
+
+
+begin
+
+--*******************************************************************
+--******************* PCI Write Configuration Address ***************
+--*******************************************************************
+
+ CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);
+
+
+ process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR)
+ begin
+
+ if CF_WR_COM = '1' and IRDY_REGn = '0' and TRDYn = '0' then
+
+ if CONFIG_ADDR = X"04" then
+ CONFIG_WRITE <= "0001";
+
+ elsif CONFIG_ADDR = X"10" then
+ CONFIG_WRITE <= "0010";
+
+ elsif CONFIG_ADDR = X"3C" then
+ CONFIG_WRITE <= "0100";
+
+-- elsif CONFIG_ADDR = X"40" then CONFIG_WRITE <= "1000";
+ else
+ CONFIG_WRITE <= "0000";
+ end if;
+ else
+ CONFIG_WRITE <= "0000";
+ end if;
+ end process;
+
+ CONF_WR_04H <= CONFIG_WRITE(0);
+ CONF_WR_10H <= CONFIG_WRITE(1);
+ CONF_WR_3CH <= CONFIG_WRITE(2);
+--CONF_WR_40H <= CONFIG_WRITE(3);
+
+end architecture CONFIG_WR_0_DESIGN;
projects / raggedstone / blobdiff