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[raggedstone] / dhwk / source / pci / config_space_header.vhd

diff --git a/dhwk/source/pci/config_space_header.vhd b/dhwk/source/pci/config_space_header.vhd
index 722b931cac03ea21acff8726c08c235b105b4267..15db761375688bbf78f5f44f9071e2e50aa0d795 100644 (file)
--- a/dhwk/source/pci/config_space_header.vhd
+++ b/dhwk/source/pci/config_space_header.vhd
@@ -27,17 +27,6 @@ end CONFIG_SPACE_HEADER;
 
 architecture SCHEMATIC of CONFIG_SPACE_HEADER is
 
 
 architecture SCHEMATIC of CONFIG_SPACE_HEADER is
 

-        constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";
-        --other comm. device
-        constant CONF_CLASS_CODE :std_logic_vector (31 downto 8) := X"078000";
-
-        signal CONF_MAX_LAT :std_logic_vector (31 downto 24);
-        signal CONF_MIN_GNT :std_logic_vector (23 downto 16);
-        signal CONF_INT_PIN :std_logic_vector (15 downto 8);
-        signal CONF_INT_LINE :std_logic_vector ( 7 downto 0);
-
-        signal CONF_BAS_ADDR_REG :std_logic_vector(31 downto 0);
-

         SIGNAL gnd : std_logic := '0';
         SIGNAL vcc : std_logic := '1';
 
         SIGNAL gnd : std_logic := '0';
         SIGNAL vcc : std_logic := '1';
 


@@ -45,11 +34,22 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
         signal CONF_WR_10H : std_logic;
         signal CONF_WR_3CH : std_logic;
         signal CONF_READ_SEL : std_logic_vector (2 downto 0);
         signal CONF_WR_10H : std_logic;
         signal CONF_WR_3CH : std_logic;
         signal CONF_READ_SEL : std_logic_vector (2 downto 0);

+        signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0);

         signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);
         signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
         signal CONF_DATA_08H : std_logic_vector (31 downto 0);
         signal CONF_DATA_00H : std_logic_vector (31 downto 0);
 
         signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);
         signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
         signal CONF_DATA_08H : std_logic_vector (31 downto 0);
         signal CONF_DATA_00H : std_logic_vector (31 downto 0);
 

+        component CONFIG_MUX_0
+                Port ( CONF_DATA_00H : In std_logic_vector (31 downto 0);
+                       CONF_DATA_04H : In std_logic_vector (31 downto 0);
+                       CONF_DATA_08H : In std_logic_vector (31 downto 0);
+                       CONF_DATA_10H : In std_logic_vector (31 downto 0);
+                       CONF_DATA_3CH : In std_logic_vector (31 downto 0);
+                       READ_SEL : In std_logic_vector (2 downto 0);
+                       CONF_DATA : Out std_logic_vector (31 downto 0) );
+        end component;
+

         component CONFIG_RD_0
                 Port ( ADDR_REG : In std_logic_vector (31 downto 0);
                        CF_RD_COM : In std_logic;
         component CONFIG_RD_0
                 Port ( ADDR_REG : In std_logic_vector (31 downto 0);
                        CF_RD_COM : In std_logic;


@@ -66,6 +66,34 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
                        CONF_WR_3CH : Out std_logic );
         end component;
 
                        CONF_WR_3CH : Out std_logic );
         end component;
 

+        component CONFIG_3CH
+                Port ( AD_REG : In std_logic_vector (31 downto 0);
+                       CBE_REGn : In std_logic_vector (3 downto 0);
+                       CONF_WR_3CH : In std_logic;
+                       PCI_CLOCK : In std_logic;
+                       PCI_RSTn : In std_logic;
+                       CONF_DATA_3CH : Out std_logic_vector (31 downto 0) );
+        end component;
+
+        component CONFIG_10H
+                Port ( AD_REG : In std_logic_vector (31 downto 0);
+                       CBE_REGn : In std_logic_vector (3 downto 0);
+                       CONF_WR_10H : In std_logic;
+                       PCI_CLOCK : In std_logic;
+                       PCI_RSTn : In std_logic;
+                       CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
+        end component;
+
+        component CONFIG_08H
+                Port ( REVISION_ID : In std_logic_vector (7 downto 0);
+                       CONF_DATA_08H : Out std_logic_vector (31 downto 0) );
+        end component;
+
+        component CONFIG_00H
+                Port ( VENDOR_ID : In std_logic_vector (15 downto 0);
+                       CONF_DATA_00H : Out std_logic_vector (31 downto 0) );
+        end component;
+

         component CONFIG_04H
                 Port ( AD_REG : In std_logic_vector (31 downto 0);
                        CBE_REGn : In std_logic_vector (3 downto 0);
         component CONFIG_04H
                 Port ( AD_REG : In std_logic_vector (31 downto 0);
                        CBE_REGn : In std_logic_vector (3 downto 0);


@@ -78,25 +106,18 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
         end component;
 
 begin
         end component;
 
 begin

-        CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
-        CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;

 
         CONF_DATA_04H <= CONF_DATA_04H_DUMMY;
 
         CONF_DATA_04H <= CONF_DATA_04H_DUMMY;

-
-        CONF_MAX_LAT <= X"00";
-        CONF_MIN_GNT <= X"00";
-        -- CONF_INT_PIN <= X"00"; -- Interrupt -
-        CONF_INT_PIN <= X"01"; -- Interrupt A
-        -- CONF_INT_PIN <= X"02"; -- Interrupt B
-        -- CONF_INT_PIN <= X"03"; -- Interrupt C
-        -- CONF_INT_PIN <= X"04"; -- Interrupt D
-        -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert
-        CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;
-
-        CONF_BAS_ADDR_REG(1 downto 0) <= "01";-- Base Address Register for "I/O"
-        CONF_BAS_ADDR_REG(3 downto 2) <= "00";-- IO Bereich = 16 BYTE
-        CONF_DATA_10H <= CONF_BAS_ADDR_REG;
-
+        CONF_DATA_10H <= CONF_DATA_10H_DUMMY;
+
+        I10 : CONFIG_MUX_0
+        Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),
+        CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),
+        CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0),
+        CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0),
+        CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0),
+        READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0),
+        CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) );

         I9 : CONFIG_RD_0
         Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
                    CF_RD_COM=>CF_RD_COM,
         I9 : CONFIG_RD_0
         Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
                    CF_RD_COM=>CF_RD_COM,


@@ -106,6 +127,24 @@ begin
                    CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
                    TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
                    CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );
                    CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
                    TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
                    CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );

+        I6 : CONFIG_3CH
+        Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+        CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+        CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK,
+        PCI_RSTn=>PCI_RSTn,
+        CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) );
+        I5 : CONFIG_10H
+        Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+        CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+        CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,
+        PCI_RSTn=>PCI_RSTn,
+        CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );
+        I4 : CONFIG_08H
+        Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0),
+        CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) );
+        I3 : CONFIG_00H
+        Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
+        CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) );

         I2 : CONFIG_04H
         Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
         CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
         I2 : CONFIG_04H
         Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
         CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),


@@ -113,56 +152,4 @@ begin
         PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,
         CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );
 
         PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,
         CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );
 

-        process (PCI_CLOCK,PCI_RSTn)
-        begin
-        if PCI_RSTn = '0' then
-                CONF_INT_LINE <= (others => '0');
-
-        elsif (rising_edge(PCI_CLOCK)) then
-                if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then
-                        CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
-                end if;
-        end if;
-        end process;
-
-        process (PCI_CLOCK,PCI_RSTn)
-        begin
-
-        -- if PCI_RSTn = '0' then CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');
-        if PCI_RSTn = '0' then
-                CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');
-
-        elsif (rising_edge(PCI_CLOCK)) then
-
-                if CONF_WR_10H = '1'and CBE_REGn(3) = '0' then
-                        CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);
-                else
-                        CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);
-                end if;
-
-                if CONF_WR_10H = '1'and CBE_REGn(2) = '0' then
-                        CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);
-                else
-                        CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);
-                end if;
-
-                if CONF_WR_10H = '1'and CBE_REGn(1) = '0' then
-                        CONF_BAS_ADDR_REG(15 downto 8) <= AD_REG(15 downto 8);
-                else
-                        CONF_BAS_ADDR_REG(15 downto 8) <= CONF_BAS_ADDR_REG(15 downto 8);
-                end if;
-
-                -- if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
-                --         CONF_BAS_ADDR_REG( 7 downto 2) <= AD_REG( 7 downto 2);
-                -- else
-                --         CONF_BAS_ADDR_REG( 7 downto 2) <= CONF_BAS_ADDR_REG( 7 downto 2);
-                -- end if;
-
-                if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
-                        CONF_BAS_ADDR_REG( 7 downto 4) <= AD_REG( 7 downto 4);
-                else
-                        CONF_BAS_ADDR_REG( 7 downto 4) <= CONF_BAS_ADDR_REG( 7 downto 4);
-                end if;
-        end if;
-        end process;

 end SCHEMATIC;
 end SCHEMATIC;