);\r
end component;\r
\r
-component wb_7seg_new\r
+component wb_fifo\r
port (\r
clk_i : in std_logic;\r
nrst_i : in std_logic;\r
wb_err_o : out std_logic;\r
wb_int_o : out std_logic;\r
\r
- DISP_SEL : inout std_logic_vector(3 downto 0);\r
- DISP_LED : out std_logic_vector(6 downto 0)\r
+ fifo_data_i : in std_logic_vector(7 downto 0);\r
+ fifo_data_o : out std_logic_vector(7 downto 0)\r
+\r
+ fifo_we_out : out std_logic;\r
+ fifo_re_out : out std_logic;\r
);\r
end component;\r
\r