]> cvs.zerfleddert.de Git - raggedstone/blobdiff - dhwk/source/pci/interrupt.vhd
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[raggedstone] / dhwk / source / pci / interrupt.vhd
index 1c1e6e8276aab897a1772288854d1c5a10f4597a..5d3b4734d46ee8ae8b2c5051579371c97ffae3eb 100644 (file)
@@ -75,7 +75,7 @@ begin
                         FF_A <= "00000000";
                         FF_B <= "00000000";
 
                         FF_A <= "00000000";
                         FF_B <= "00000000";
 
-                elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                elsif (rising_edge(PCI_CLOCK)) then
                         if (RESET = '1') then
                                 SET <= "00000000";
                                 FF_A <= "00000000";
                         if (RESET = '1') then
                                 SET <= "00000000";
                                 FF_A <= "00000000";
@@ -105,7 +105,7 @@ begin
                 if (PCI_RSTn = '0') then
                         REG <= "00000000";
 
                 if (PCI_RSTn = '0') then
                         REG <= "00000000";
 
-                elsif(PCI_CLOCK'event and PCI_CLOCK = '1') then
+                elsif(rising_edge(PCI_CLOCK)) then
                         if(RESET = '1') then
                                 REG <= "00000000";
 
                         if(RESET = '1') then
                                 REG <= "00000000";
 
@@ -120,8 +120,8 @@ begin
                 end if;
         end process;
 
                 end if;
         end process;
 
-        SIG_PROPAGATE_INT <=
-        (REG(0) AND INT_MASKE(0))
+        SIG_PROPAGATE_INT <= (not TAST_SETn)
+        OR (REG(0) AND INT_MASKE(0))
         OR (REG(1) AND INT_MASKE(1))
         OR (REG(2) AND INT_MASKE(2))
         OR (REG(3) AND INT_MASKE(3))
         OR (REG(1) AND INT_MASKE(1))
         OR (REG(2) AND INT_MASKE(2))
         OR (REG(3) AND INT_MASKE(3))
@@ -132,7 +132,7 @@ begin
 
         process (PCI_CLOCK)
         begin
 
         process (PCI_CLOCK)
         begin
-                if(PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if(rising_edge(PCI_CLOCK)) then
                         SIG_PROPAGATE_INT_SECOND <= not SIG_PROPAGATE_INT;
                 end if;
         end process;
                         SIG_PROPAGATE_INT_SECOND <= not SIG_PROPAGATE_INT;
                 end if;
         end process;
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