add cable help

[raggedstone] / dhwk / source / pci / top.vhd

diff --git a/dhwk/source/pci/top.vhd b/dhwk/source/pci/top.vhd
index e16f5123d7d835ebfdc14986a343ade147b95765..86cd575d3ab1643a43de8b2cd2d4bdd82a864843 100644 (file)
--- a/dhwk/source/pci/top.vhd
+++ b/dhwk/source/pci/top.vhd
@@ -97,8 +97,10 @@ architecture SCHEMATIC of dhwk is
         signal watch_PCI_PERRn : std_logic;
         signal watch_PCI_REQn : std_logic;
         signal control0 : std_logic_vector(35 downto 0);
+        signal control1 : std_logic_vector(35 downto 0);
         signal data : std_logic_vector(95 downto 0);
         signal trig0 : std_logic_vector(31 downto 0);
+       signal vio_async_out : std_logic_vector(0 downto 0);
 
         component MESS_1_TB
                 Port ( DEVSELn : In std_logic;
@@ -232,7 +234,8 @@ architecture SCHEMATIC of dhwk is
         component icon
                 port
                 (
-                        control0 : out std_logic_vector(35 downto 0)
+                        control0 : out std_logic_vector(35 downto 0);
+                        control1 : out std_logic_vector(35 downto 0)
                 );
         end component;
 
@@ -246,16 +249,25 @@ architecture SCHEMATIC of dhwk is
                 );
         end component;
 
+       component vio
+               port
+               (
+                       control : in std_logic_vector(35 downto 0);
+                       async_out : out std_logic_vector(0 downto 0)
+               );
+       end component;
+
 
 begin
         watch_PCI_REQn <= '1';
         SERIAL_IN <= SERIAL_OUT;
         SPC_RDY_IN <= SPC_RDY_OUT;
         LED_2 <= not PCI_RSTn;
-        LED_3 <= PCI_IDSEL;
+        LED_3 <= not PCI_IDSEL;
         LED_4 <= not PCI_FRAMEn;
         LED_5 <= not watch_PCI_INTAn;
-        PCI_INTAn <= watch_PCI_INTAn;
+        PCI_INTAn <= watch_PCI_INTAn and (not vio_async_out(0));
+
         trig0(31 downto 0) <= (
         0 => watch_PCI_INTAn,
         1 => R_FIFO_READn,
@@ -263,6 +275,7 @@ begin
         3 => S_FIFO_READn,
         4 => S_FIFO_WRITEn,
         5 => PCI_RSTn,
+       6 => PCI_IDSEL,
         16 => PCI_AD(0),
         17 => PCI_AD(1),
         18 => PCI_AD(2),
@@ -411,7 +424,8 @@ begin
         i_icon : icon
         port map
         (
-                control0 => control0
+                control0 => control0,
+                control1 => control1
         );
 
         i_ila : ila
@@ -422,4 +436,11 @@ begin
                 data => data,
                 trig0 => trig0
         );
+
+       i_vio : vio
+       port map
+       (
+               control => control1,
+               async_out => vio_async_out
+       );
 end SCHEMATIC;