--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 29.08.2006\r
--- File: MESS_1_TB.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity MESS_1_TB is\r
- port\r
- (\r
- KONST_1 :in std_logic;\r
- PCI_IDSEL :in std_logic;\r
- DEVSELn :in std_logic;\r
- INTAn :in std_logic;\r
- REG_OUT_XX7 :in std_logic_vector(7 downto 0);\r
- TB_PCI_IDSEL :out std_logic;\r
- TB_DEVSELn :out std_logic;\r
- TB_INTAn :out std_logic\r
- );\r
-end entity MESS_1_TB;\r
-\r
-architecture MESS_1_TB_DESIGN of MESS_1_TB is\r
- \r
-begin\r
-\r
- TB_PCI_IDSEL <= PCI_IDSEL and KONST_1;\r
-\r
- TB_INTAn <= INTAn and KONST_1; \r
- \r
- TB_DEVSELn <= DEVSELn when REG_OUT_XX7(7) = '0' else (not REG_OUT_XX7(6));\r
-\r
-end architecture MESS_1_TB_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 29.08.2006
+-- File: MESS_1_TB.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity MESS_1_TB is
+ port
+ (
+ KONST_1 :in std_logic;
+ PCI_IDSEL :in std_logic;
+ DEVSELn :in std_logic;
+ INTAn :in std_logic;
+ REG_OUT_XX7 :in std_logic_vector(7 downto 0);
+ TB_PCI_IDSEL :out std_logic;
+ TB_DEVSELn :out std_logic;
+ TB_INTAn :out std_logic
+ );
+end entity MESS_1_TB;
+
+architecture MESS_1_TB_DESIGN of MESS_1_TB is
+
+begin
+
+ TB_PCI_IDSEL <= PCI_IDSEL and KONST_1;
+
+ TB_INTAn <= INTAn and KONST_1;
+
+ TB_DEVSELn <= DEVSELn when REG_OUT_XX7(7) = '0' else (not REG_OUT_XX7(6));
+
+end architecture MESS_1_TB_DESIGN;