SERIAL_OUT : Out std_logic;\r
SPC_RDY_OUT : Out std_logic;\r
SR_ERROR : Out std_logic;\r
- SYNC_FLAG : Out std_logic_vector (7 downto 0) );\r
+ SYNC_FLAG : Out std_logic_vector (7 downto 0));\r
end FIFO_CONTROL;\r
\r
architecture SCHEMATIC of FIFO_CONTROL is\r