dos2unix *.vhd

[raggedstone] / dhwk / source / verg_8.vhd

diff --git a/dhwk/source/verg_8.vhd b/dhwk/source/verg_8.vhd
index 294aac5552cc2196c3fcb743558539d87860d502..618a0cca22168df6ac8babd88cfe132c3ac80a55 100644 (file)
--- a/dhwk/source/verg_8.vhd
+++ b/dhwk/source/verg_8.vhd
@@ -1,28 +1,28 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: VERG_8.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-\r
-entity VERG_8 is\r
-       port\r
-       (\r
-       GLEICH                  :in             std_logic_vector(7 downto 0);\r
-       GLEICH_OUT      :out    std_logic\r
-       );\r
-\r
-end entity VERG_8 ;\r
-\r
-architecture VERG_8_DESIGN of VERG_8 is\r
- \r
-\r
-begin\r
-\r
---     GLEICH(0) nicht noetig. Addr-Bereich = 16 Byte\r
-\r
---     GLEICH_OUT      <=      '1'     when    GLEICH(7 downto 0)      =       "11111111"      else    '0';    \r
-               GLEICH_OUT      <=      '1'     when    GLEICH(7 downto 1)      =       "1111111"               else    '0'; \r
- \r
-end architecture VERG_8_DESIGN ;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VERG_8.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity VERG_8 is
+       port
+       (
+       GLEICH                  :in             std_logic_vector(7 downto 0);
+       GLEICH_OUT      :out    std_logic
+       );
+
+end entity VERG_8 ;
+
+architecture VERG_8_DESIGN of VERG_8 is
+ 
+
+begin
+
+--     GLEICH(0) nicht noetig. Addr-Bereich = 16 Byte
+
+--     GLEICH_OUT      <=      '1'     when    GLEICH(7 downto 0)      =       "11111111"      else    '0';    
+               GLEICH_OUT      <=      '1'     when    GLEICH(7 downto 1)      =       "1111111"               else    '0'; 
+ 
+end architecture VERG_8_DESIGN ;