update to EDK 9.1i

[raggedstone] / ethernet / ethernet.ucf

diff --git a/ethernet/ethernet.ucf b/ethernet/ethernet.ucf
index 3ad29427632e867416784086b0a6dae52282a602..395303ebb7af8da4c26f0d4b577be46e978ca34a 100644 (file)
--- a/ethernet/ethernet.ucf
+++ b/ethernet/ethernet.ucf
@@ -49,7 +49,6 @@ NET "PCI_PAR"  LOC = "A9" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_REQn"  LOC = "C18" | IOSTANDARD = PCI33_3 | SLEW = FAST ;
 NET "PCI_GNTn"  LOC = "D18" | IOSTANDARD = PCI33_3 ;
 
-NET "INT_CLOCK"  LOC = "AA11" | IOSTANDARD = PCI33_3 ;
 NET "MTX_CLK_PAD_I"  LOC = "M2" | IOSTANDARD = LVCMOS33;
 
 NET "MTXD_PAD_O<0>"  LOC = "M5" | IOSTANDARD = LVCMOS33;
@@ -74,3 +73,22 @@ NET "MCOLL_PAD_I" LOC = "N2" | IOSTANDARD = LVCMOS33;
 NET "MCRS_PAD_I"  LOC = "U3" | IOSTANDARD = LVCMOS33;
 NET "MD_PAD_IO"   LOC = "Y1" | IOSTANDARD = LVCMOS33;
 NET "MDC_PAD_O"   LOC = "U2" | IOSTANDARD = LVCMOS33;
+
+NET "PHY_CLOCK"   LOC = "L5" | IOSTANDARD = LVCMOS33;
+
+NET "LED_2"  LOC = "AB5"  | IOSTANDARD = LVTTL | DRIVE = 24 ;
+
+INST "eth_dcm/DCM_INST" CLK_FEEDBACK = 1X;
+INST "eth_dcm/DCM_INST" CLKDV_DIVIDE = 2.0;
+INST "eth_dcm/DCM_INST" CLKFX_DIVIDE = 29;
+INST "eth_dcm/DCM_INST" CLKFX_MULTIPLY = 22;
+INST "eth_dcm/DCM_INST" CLKIN_DIVIDE_BY_2 = FALSE;
+INST "eth_dcm/DCM_INST" CLKIN_PERIOD = 30.303;
+INST "eth_dcm/DCM_INST" CLKOUT_PHASE_SHIFT = NONE;
+INST "eth_dcm/DCM_INST" DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
+INST "eth_dcm/DCM_INST" DFS_FREQUENCY_MODE = LOW;
+INST "eth_dcm/DCM_INST" DLL_FREQUENCY_MODE = LOW;
+INST "eth_dcm/DCM_INST" DUTY_CYCLE_CORRECTION = TRUE;
+INST "eth_dcm/DCM_INST" FACTORY_JF = 8080;
+INST "eth_dcm/DCM_INST" PHASE_SHIFT = 0;
+INST "eth_dcm/DCM_INST" STARTUP_WAIT = FALSE;