PCI_IDSEL : In std_logic;\r
PCI_IRDYn : In std_logic;\r
PCI_RSTn : In std_logic;\r
- R_EFn : In std_logic;\r
- R_FFn : In std_logic;\r
- R_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
- R_HFn : In std_logic;\r
- S_EFn : In std_logic;\r
- S_FFn : In std_logic;\r
- S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
- S_HFn : In std_logic;\r
- SERIAL_IN : In std_logic;\r
- SPC_RDY_IN : In std_logic;\r
+-- SERIAL_IN : In std_logic;\r
+-- SPC_RDY_IN : In std_logic;\r
TAST_RESn : In std_logic;\r
TAST_SETn : In std_logic;\r
+ LED_2 : out std_logic;\r
+ LED_3 : out std_logic;\r
+ LED_4 : out std_logic;\r
+ LED_5 : out std_logic;\r
PCI_AD : InOut std_logic_vector (31 downto 0);\r
PCI_PAR : InOut std_logic;\r
PCI_DEVSELn : Out std_logic;\r
PCI_SERRn : Out std_logic;\r
PCI_STOPn : Out std_logic;\r
PCI_TRDYn : Out std_logic;\r
- R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
- R_FIFO_READn : Out std_logic;\r
- R_FIFO_RESETn : Out std_logic;\r
- R_FIFO_RTn : Out std_logic;\r
- R_FIFO_WRITEn : Out std_logic;\r
- S_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
- S_FIFO_READn : Out std_logic;\r
- S_FIFO_RESETn : Out std_logic;\r
- S_FIFO_RTn : Out std_logic;\r
- S_FIFO_WRITEn : Out std_logic;\r
- SERIAL_OUT : Out std_logic;\r
- SPC_RDY_OUT : Out std_logic;\r
+-- SERIAL_OUT : Out std_logic;\r
+-- SPC_RDY_OUT : Out std_logic;\r
TB_IDSEL : Out std_logic;\r
TB_nDEVSEL : Out std_logic;\r
TB_nINTA : Out std_logic );\r
signal READ_SEL : std_logic_vector (1 downto 0);\r
signal AD_REG : std_logic_vector (31 downto 0);\r
signal REG_OUT_XX7 : std_logic_vector (7 downto 0);\r
+ signal R_EFn : std_logic;\r
+ signal R_FFn : std_logic;\r
+ signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
+ signal R_HFn : std_logic;\r
+ signal S_EFn : std_logic;\r
+ signal S_FFn : std_logic;\r
+ signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
+ signal S_HFn : std_logic;\r
+ signal R_FIFO_D_IN : std_logic_vector (7 downto 0);\r
+ signal R_FIFO_READn : std_logic;\r
+ signal R_FIFO_RESETn : std_logic;\r
+ signal R_FIFO_RTn : std_logic;\r
+ signal R_FIFO_WRITEn : std_logic;\r
+ signal S_FIFO_D_IN : std_logic_vector (7 downto 0);\r
+ signal S_FIFO_READn : std_logic;\r
+ signal S_FIFO_RESETn : std_logic;\r
+ signal S_FIFO_RTn : std_logic;\r
+ signal S_FIFO_WRITEn : std_logic;\r
+ signal SERIAL_IN : std_logic;\r
+ signal SPC_RDY_IN : std_logic;\r
+ signal SERIAL_OUT : std_logic;\r
+ signal SPC_RDY_OUT : std_logic;\r
+ signal watch : std_logic;\r
+ signal control0 : std_logic_vector(35 downto 0);\r
+ signal data : std_logic_vector(95 downto 0);\r
+ signal trig0 : std_logic_vector(31 downto 0);\r
\r
component MESS_1_TB\r
Port ( DEVSELn : In std_logic;\r
WRITE_XX7_6 : Out std_logic );\r
end component;\r
\r
+component fifo_generator_v3_2\r
+ port (\r
+ clk: IN std_logic;\r
+ din: IN std_logic_VECTOR(7 downto 0);\r
+ rd_en: IN std_logic;\r
+ rst: IN std_logic;\r
+ wr_en: IN std_logic;\r
+ almost_empty: OUT std_logic;\r
+ almost_full: OUT std_logic;\r
+ dout: OUT std_logic_VECTOR(7 downto 0);\r
+ empty: OUT std_logic;\r
+ full: OUT std_logic;\r
+ prog_full: OUT std_logic);\r
+end component;\r
+\r
+component icon\r
+port\r
+ (\r
+ control0 : out std_logic_vector(35 downto 0)\r
+ );\r
+end component;\r
+\r
+ component ila\r
+ port\r
+ (\r
+ control : in std_logic_vector(35 downto 0);\r
+ clk : in std_logic;\r
+ data : in std_logic_vector(95 downto 0);\r
+ trig0 : in std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
begin\r
+ SERIAL_IN <= SERIAL_OUT;\r
+ SPC_RDY_IN <= SPC_RDY_OUT;\r
+ LED_2 <= TAST_RESn;\r
+ LED_3 <= TAST_SETn;\r
+ LED_4 <= '0';\r
+ LED_5 <= not watch;\r
+ PCI_INTAn <= watch;\r
+ trig0(31 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');\r
+ data(0) <= watch;\r
+ \r
+ data(1) <= R_EFn;\r
+ data(2) <= R_HFn;\r
+ data(3) <= R_FFn;\r
+ data(4) <= R_FIFO_READn;\r
+ data(5) <= R_FIFO_RESETn;\r
+ data(6) <= R_FIFO_RTn;\r
+ data(7) <= R_FIFO_WRITEn;\r
+ data(8) <= S_EFn;\r
+ data(9) <= S_HFn;\r
+ data(10) <= S_FFn;\r
+ data(11) <= S_FIFO_READn;\r
+ data(12) <= S_FIFO_RESETn;\r
+ data(13) <= S_FIFO_RTn;\r
+ data(14) <= S_FIFO_WRITEn;\r
+ data(15) <= SERIAL_IN;\r
+ data(16) <= SPC_RDY_IN;\r
+ data(17) <= SERIAL_OUT;\r
+ data(18) <= SPC_RDY_OUT;\r
+ data(26 downto 19) <= S_FIFO_Q_OUT;\r
+ data(34 downto 27) <= R_FIFO_Q_OUT;\r
+ data(66 downto 35) <= PCI_AD(31 downto 0);\r
+ data(70 downto 67) <= PCI_CBEn(3 downto 0);\r
\r
I19 : MESS_1_TB\r
Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),\r
TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,\r
TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
- INTAn=>INTAn, PCI_INTAn=>PCI_INTAn );\r
+ INTAn=>INTAn, PCI_INTAn=>watch);\r
I14 : FIFO_CONTROL\r
Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,\r
FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,\r
WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
WRITE_XX7_6=>WRITE_XX7_6 );\r
\r
+receive_fifo : fifo_generator_v3_2\r
+ port map (\r
+ clk => PCI_CLOCK,\r
+ din => R_FIFO_D_IN,\r
+ rd_en => not R_FIFO_READn,\r
+ rst => not R_FIFO_RESETn,\r
+ wr_en => not R_FIFO_WRITEn,\r
+ dout => R_FIFO_Q_OUT,\r
+ empty => R_EFn,\r
+ full => R_FFn,\r
+ prog_full => R_HFn);\r
+\r
+send_fifo : fifo_generator_v3_2\r
+ port map (\r
+ clk => PCI_CLOCK,\r
+ din => S_FIFO_D_IN,\r
+ rd_en => not S_FIFO_READn,\r
+ rst => not S_FIFO_RESETn,\r
+ wr_en => not S_FIFO_WRITEn,\r
+ dout => S_FIFO_Q_OUT,\r
+ empty => S_EFn,\r
+ full => S_FFn,\r
+ prog_full => S_HFn);\r
+\r
+ i_icon : icon\r
+ port map\r
+ (\r
+ control0 => control0\r
+ );\r
+\r
+ i_ila : ila\r
+ port map\r
+ (\r
+ control => control0,\r
+ clk => PCI_CLOCK,\r
+ data => data,\r
+ trig0 => trig0\r
+ );\r
end SCHEMATIC;\r
projects / raggedstone / blobdiff