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[raggedstone] / dhwk / source / top.vhd

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index e0ad093580c50e835a82c53b1a1f1ee3afc3aca4..a79c47032468b8b59def86cd4406abdbf882ad5f 100644 (file)
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -16,18 +16,14 @@ entity dhwk is
              PCI_IDSEL : In    std_logic;\r
              PCI_IRDYn : In    std_logic;\r
              PCI_RSTn : In    std_logic;\r
-               R_EFn : In    std_logic;\r
-               R_FFn : In    std_logic;\r
-             R_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
-               R_HFn : In    std_logic;\r
-               S_EFn : In    std_logic;\r
-               S_FFn : In    std_logic;\r
-             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
-               S_HFn : In    std_logic;\r
-             SERIAL_IN : In    std_logic;\r
-             SPC_RDY_IN : In    std_logic;\r
+--             SERIAL_IN : In    std_logic;\r
+--             SPC_RDY_IN : In    std_logic;\r
              TAST_RESn : In    std_logic;\r
              TAST_SETn : In    std_logic;\r
+             LED_2 : out    std_logic;\r
+             LED_3 : out    std_logic;\r
+             LED_4 : out    std_logic;\r
+             LED_5 : out    std_logic;\r
               PCI_AD : InOut std_logic_vector (31 downto 0);\r
              PCI_PAR : InOut std_logic;\r
              PCI_DEVSELn : Out   std_logic;\r
@@ -36,18 +32,8 @@ entity dhwk is
              PCI_SERRn : Out   std_logic;\r
              PCI_STOPn : Out   std_logic;\r
              PCI_TRDYn : Out   std_logic;\r
-             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
-             R_FIFO_READn : Out   std_logic;\r
-             R_FIFO_RESETn : Out   std_logic;\r
-             R_FIFO_RTn : Out   std_logic;\r
-             R_FIFO_WRITEn : Out   std_logic;\r
-             S_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
-             S_FIFO_READn : Out   std_logic;\r
-             S_FIFO_RESETn : Out   std_logic;\r
-             S_FIFO_RTn : Out   std_logic;\r
-             S_FIFO_WRITEn : Out   std_logic;\r
-             SERIAL_OUT : Out   std_logic;\r
-             SPC_RDY_OUT : Out   std_logic;\r
+--             SERIAL_OUT : Out   std_logic;\r
+--             SPC_RDY_OUT : Out   std_logic;\r
              TB_IDSEL : Out   std_logic;\r
              TB_nDEVSEL : Out   std_logic;\r
              TB_nINTA : Out   std_logic );\r
@@ -82,6 +68,29 @@ architecture SCHEMATIC of dhwk is
    signal READ_SEL : std_logic_vector (1 downto 0);\r
    signal   AD_REG : std_logic_vector (31 downto 0);\r
    signal REG_OUT_XX7 : std_logic_vector (7 downto 0);\r
+   signal R_EFn : std_logic;\r
+   signal R_FFn : std_logic;\r
+   signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
+   signal R_HFn : std_logic;\r
+   signal S_EFn : std_logic;\r
+   signal S_FFn : std_logic;\r
+   signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
+   signal S_HFn : std_logic;\r
+   signal R_FIFO_D_IN : std_logic_vector (7 downto 0);\r
+   signal R_FIFO_READn : std_logic;\r
+   signal R_FIFO_RESETn : std_logic;\r
+   signal R_FIFO_RTn : std_logic;\r
+   signal R_FIFO_WRITEn : std_logic;\r
+   signal S_FIFO_D_IN : std_logic_vector (7 downto 0);\r
+   signal S_FIFO_READn : std_logic;\r
+   signal S_FIFO_RESETn : std_logic;\r
+   signal S_FIFO_RTn : std_logic;\r
+   signal S_FIFO_WRITEn : std_logic;\r
+   signal SERIAL_IN : std_logic;\r
+   signal SPC_RDY_IN : std_logic;\r
+   signal SERIAL_OUT : std_logic;\r
+   signal SPC_RDY_OUT : std_logic;\r
+   signal watch : std_logic;\r
 \r
    component MESS_1_TB\r
       Port ( DEVSELn : In    std_logic;\r
@@ -197,7 +206,29 @@ architecture SCHEMATIC of dhwk is
              WRITE_XX7_6 : Out   std_logic );\r
    end component;\r
 \r
+component fifo_generator_v3_2\r
+        port (\r
+        clk: IN std_logic;\r
+        din: IN std_logic_VECTOR(7 downto 0);\r
+        rd_en: IN std_logic;\r
+        rst: IN std_logic;\r
+        wr_en: IN std_logic;\r
+        almost_empty: OUT std_logic;\r
+        almost_full: OUT std_logic;\r
+        dout: OUT std_logic_VECTOR(7 downto 0);\r
+        empty: OUT std_logic;\r
+        full: OUT std_logic;\r
+        prog_full: OUT std_logic);\r
+end component;\r
+\r
 begin\r
+       SERIAL_IN <= SERIAL_OUT;\r
+       SPC_RDY_IN <= SPC_RDY_OUT;\r
+       LED_2 <= TAST_RESn;\r
+       LED_3 <= TAST_SETn;\r
+       LED_4 <= '0';\r
+       LED_5 <= not watch;\r
+       PCI_INTAn <= watch;\r
 \r
    I19 : MESS_1_TB\r
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
@@ -218,7 +249,7 @@ begin
                  READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),\r
                  TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,\r
                  TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
-                 INTAn=>INTAn, PCI_INTAn=>PCI_INTAn );\r
+                 INTAn=>INTAn, PCI_INTAn=>watch);\r
    I14 : FIFO_CONTROL\r
       Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,\r
                  FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,\r
@@ -267,4 +298,27 @@ begin
                  WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
                  WRITE_XX7_6=>WRITE_XX7_6 );\r
 \r
+receive_fifo : fifo_generator_v3_2\r
+                port map (\r
+                        clk => PCI_CLOCK,\r
+                        din => R_FIFO_D_IN,\r
+                        rd_en => not R_FIFO_READn,\r
+                        rst => not R_FIFO_RESETn,\r
+                        wr_en => not R_FIFO_WRITEn,\r
+                        dout => R_FIFO_Q_OUT,\r
+                        empty => R_EFn,\r
+                        full => R_FFn,\r
+                        prog_full => R_HFn);\r
+\r
+send_fifo : fifo_generator_v3_2\r
+                port map (\r
+                        clk => PCI_CLOCK,\r
+                        din => S_FIFO_D_IN,\r
+                        rd_en => not S_FIFO_READn,\r
+                        rst => not S_FIFO_RESETn,\r
+                        wr_en => not S_FIFO_WRITEn,\r
+                        dout => S_FIFO_Q_OUT,\r
+                        empty => S_EFn,\r
+                        full => S_FFn,\r
+                        prog_full => S_HFn);\r
 end SCHEMATIC;\r