use IEEE.std_logic_1164.all;
entity IO_WR_SEL is
- port
- (
- IO_WR_COM :in std_logic;
- IRDY_REGn :in std_logic;
- TRDYn :in std_logic;
- ADDR_REG :in std_logic_vector(31 downto 0);
- CBE_REGn :in std_logic_vector( 3 downto 0);
- WRITE_XX1_0 :out std_logic;
- WRITE_XX3_2 :out std_logic;
- WRITE_XX5_4 :out std_logic;
- WRITE_XX7_6 :out std_logic
- );
+ port
+ (
+ IO_WR_COM :in std_logic;
+ IRDY_REGn :in std_logic;
+ TRDYn :in std_logic;
+ ADDR_REG :in std_logic_vector(31 downto 0);
+ CBE_REGn :in std_logic_vector( 3 downto 0);
+ WRITE_XX1_0 :out std_logic;
+ WRITE_XX3_2 :out std_logic;
+ WRITE_XX5_4 :out std_logic;
+ WRITE_XX7_6 :out std_logic
+ );
end entity IO_WR_SEL;
---PCI Byte Enable
---C/BE[3..0] gueltige Datenbits
+--PCI Byte Enable
+--C/BE[3..0] gueltige Datenbits
-------------------------------
--- 0000 AD 31..0
--- 1000 AD 23..0
--- 1100 AD 15..0
--- 1110 AD 7..0
--- 0011 AD 31..16
+-- 0000 AD 31..0
+-- 1000 AD 23..0
+-- 1100 AD 15..0
+-- 1110 AD 7..0
+-- 0011 AD 31..16
architecture IO_WR_SEL_DESIGN of IO_WR_SEL is
- signal WR_ENA :std_logic;
- signal ADDR :std_logic_vector( 5 downto 0);
+ signal WR_ENA :std_logic;
+ signal ADDR :std_logic_vector( 5 downto 0);
begin
- WR_ENA <= '1' when
- IO_WR_COM = '1' and
- IRDY_REGn = '0' and
- TRDYn = '0' else '0';
+ WR_ENA <= '1' when
+ IO_WR_COM = '1' and
+ IRDY_REGn = '0' and
+ TRDYn = '0' else '0';
+ ADDR <= ADDR_REG(3) & ADDR_REG(2) & CBE_REGn;
- ADDR <= ADDR_REG(3) & ADDR_REG(2) & CBE_REGn;
+ WRITE_XX1_0 <= '1' when WR_ENA = '1' and ADDR = "001100" else '0';
+ WRITE_XX3_2 <= '1' when WR_ENA = '1' and ADDR = "000011" else '0';
+ WRITE_XX5_4 <= '1' when WR_ENA = '1' and ADDR = "011100" else '0';
+ WRITE_XX7_6 <= '1' when WR_ENA = '1' and ADDR = "010011" else '0';
-
- WRITE_XX1_0 <= '1' when WR_ENA = '1' and ADDR = "001100" else '0';
- WRITE_XX3_2 <= '1' when WR_ENA = '1' and ADDR = "000011" else '0';
- WRITE_XX5_4 <= '1' when WR_ENA = '1' and ADDR = "011100" else '0';
- WRITE_XX7_6 <= '1' when WR_ENA = '1' and ADDR = "010011" else '0';
-
end architecture IO_WR_SEL_DESIGN;