--- $Id: fifo_io_control.vhd,v 1.2 2007-03-11 08:04:56 sithglan Exp $
+-- $Id: fifo_io_control.vhd,v 1.3 2007-03-11 08:44:31 sithglan Exp $
library IEEE;
use IEEE.std_logic_1164.all;
entity FIFO_IO_CONTROL is
- port
- (
- PCI_CLOCK :in std_logic;
- WRITE_XX1_0 :in std_logic; -- PCI Write
- FIFO_RDn :in std_logic; -- FIFO Read (low active)
- RESET :in std_logic;
- SYNC_FLAG_1 :in std_logic; -- Recv FIFO Empty (low active)
- SYNC_FLAG_7 :in std_logic; -- Send FIFO Full (low active)
- S_FIFO_RESETn :out std_logic; -- Send FIFO Reset (low active)
- R_FIFO_RESETn :out std_logic; -- Recv FIFO Reset (low active)
- S_FIFO_WRITEn :out std_logic; -- Send FIFO Write (low active)
- R_FIFO_READn :out std_logic; -- Recv FIFO Read (low active)
- S_FIFO_RETRANSMITn :out std_logic; -- Send FIFO Retransmit (low active)
- R_FIFO_RETRANSMITn :out std_logic; -- Recv FIFO Retransmit (low active)
- S_ERROR :out std_logic; -- Send ERROR
- R_ERROR :out std_logic; -- Recv ERROR
- SR_ERROR :out std_logic -- Send / Recv Error
- );
+ port
+ (
+ PCI_CLOCK :in std_logic;
+ WRITE_XX1_0 :in std_logic; -- PCI Write
+ FIFO_RDn :in std_logic; -- FIFO Read (low active)
+ RESET :in std_logic;
+ SYNC_FLAG_1 :in std_logic; -- Recv FIFO Empty (low active)
+ SYNC_FLAG_7 :in std_logic; -- Send FIFO Full (low active)
+ S_FIFO_RESETn :out std_logic; -- Send FIFO Reset (low active)
+ R_FIFO_RESETn :out std_logic; -- Recv FIFO Reset (low active)
+ S_FIFO_WRITEn :out std_logic; -- Send FIFO Write (low active)
+ R_FIFO_READn :out std_logic; -- Recv FIFO Read (low active)
+ S_FIFO_RETRANSMITn :out std_logic; -- Send FIFO Retransmit (low active)
+ R_FIFO_RETRANSMITn :out std_logic; -- Recv FIFO Retransmit (low active)
+ S_ERROR :out std_logic; -- Send ERROR
+ R_ERROR :out std_logic; -- Recv ERROR
+ SR_ERROR :out std_logic -- Send / Recv Error
+ );
end entity FIFO_IO_CONTROL;
architecture FIFO_IO_CONTROL_DESIGN of FIFO_IO_CONTROL is
-signal SIG_S_ERROR :std_logic; -- Send Error
-signal SIG_R_ERROR :std_logic; -- Recv Error
+ signal SIG_S_ERROR :std_logic; -- Send Error
+ signal SIG_R_ERROR :std_logic; -- Recv Error
begin
--- FIFO Write
+ -- FIFO Write
- process (PCI_CLOCK)
- begin
- if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ process (PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK = '1') then
if (RESET = '1') then
S_FIFO_WRITEn <= '1';
- SIG_S_ERROR <= '0';
+ SIG_S_ERROR <= '0';
elsif (WRITE_XX1_0 = '0') then
S_FIFO_WRITEn <= '1';
S_FIFO_WRITEn <= '0';
SIG_S_ERROR <= '0';
end if;
- end if;
- end if;
- end process;
+ end if;
+ end if;
+ end process;
+
+ S_ERROR <= SIG_S_ERROR;
- S_ERROR <= SIG_S_ERROR;
-
--- FIFO Read
+ -- FIFO Read
- R_FIFO_READn <= FIFO_RDn;
+ R_FIFO_READn <= FIFO_RDn;
-- Receive Error
-process (PCI_CLOCK)
-begin
- if (PCI_CLOCK'event and PCI_CLOCK ='1') then
- if (RESET = '1') then
- SIG_R_ERROR <= '0';
+ process (PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK ='1') then
+ if (RESET = '1') then
+ SIG_R_ERROR <= '0';
- elsif (FIFO_RDn = '0' and SYNC_FLAG_1 = '0') then
- SIG_R_ERROR <= '1';
+ elsif (FIFO_RDn = '0' and SYNC_FLAG_1 = '0') then
+ SIG_R_ERROR <= '1';
+ end if;
end if;
- end if;
-end process;
+ end process;
- R_ERROR <= SIG_R_ERROR;
+ R_ERROR <= SIG_R_ERROR;
-- Send or Receive Error
-process (PCI_CLOCK)
-begin
- if (PCI_CLOCK'event and PCI_CLOCK ='1') then
- SR_ERROR <= SIG_S_ERROR or SIG_R_ERROR;
- end if;
-end process;
+ process (PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK ='1') then
+ SR_ERROR <= SIG_S_ERROR or SIG_R_ERROR;
+ end if;
+ end process;
-- FIFO Reset
-process (PCI_CLOCK)
-begin
- if (PCI_CLOCK'event and PCI_CLOCK ='1') then
- S_FIFO_RESETn <= not RESET;
- R_FIFO_RESETn <= not RESET;
- end if;
-end process;
+ process (PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK ='1') then
+ S_FIFO_RESETn <= not RESET;
+ R_FIFO_RESETn <= not RESET;
+ end if;
+ end process;
-- FIFO Retransmit
-process (PCI_CLOCK)
-begin
- if (PCI_CLOCK'event and PCI_CLOCK ='1') then
- S_FIFO_RETRANSMITn <= '1';
- R_FIFO_RETRANSMITn <= '1';
- end if;
-end process;
-
+ process (PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK ='1') then
+ S_FIFO_RETRANSMITn <= '1';
+ R_FIFO_RETRANSMITn <= '1';
+ end if;
+ end process;
+
end architecture FIFO_IO_CONTROL_DESIGN;