-- VHDL model created from schematic parity.sch -- Jan 09 09:34:12 2007
---LIBRARY vanmacro;
---USE vanmacro.components.ALL;
LIBRARY ieee;
---LIBRARY generics;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
---USE generics.components.ALL;
entity PARITY is
- Port ( OE_PCI_PAR : In std_logic;
- OE_PCI_PERR : In std_logic;
- PA_ER_RE : In std_logic;
- PAR_IN : In std_logic_vector (35 downto 0);
- PAR_REG : In std_logic;
- PCI_CLOCK : In std_logic;
- PCI_RSTn : In std_logic;
- PERR_CHECK : In std_logic;
- SERR_CHECK : In std_logic;
- SERR_ENA : In std_logic;
- PCI_PAR : InOut std_logic;
- PCI_PERRn : Out std_logic;
- PCI_SERRn : Out std_logic;
- PERR : Out std_logic;
- SERR : Out std_logic );
+ Port ( OE_PCI_PAR : In std_logic;
+ OE_PCI_PERR : In std_logic;
+ PA_ER_RE : In std_logic;
+ PAR_IN : In std_logic_vector (35 downto 0);
+ PAR_REG : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ PERR_CHECK : In std_logic;
+ SERR_CHECK : In std_logic;
+ SERR_ENA : In std_logic;
+ PCI_PAR : InOut std_logic;
+ PCI_PERRn : Out std_logic;
+ PCI_SERRn : Out std_logic;
+ PERR : Out std_logic;
+ SERR : Out std_logic );
end PARITY;
architecture SCHEMATIC of PARITY is
- SIGNAL gnd : std_logic := '0';
- SIGNAL vcc : std_logic := '1';
+ SIGNAL gnd : std_logic := '0';
+ SIGNAL vcc : std_logic := '1';
- signal PAR_OUT : std_logic_vector (10 downto 0);
+ signal PAR_OUT : std_logic_vector (10 downto 0);
- component PARITY_OUT
- Port ( OE_PCI_PAR : In std_logic;
- OE_PCI_PERR : In std_logic;
- PA_ER_RE : In std_logic;
- PAR_IN : In std_logic_vector (2 downto 0);
- PAR_REG : In std_logic;
- PCI_CLOCK : In std_logic;
- PCI_PAR_IN : In std_logic;
- PCI_RSTn : In std_logic;
- PERR_CHECK : In std_logic;
- SERR_CHECK : In std_logic;
- SERR_ENA : In std_logic;
- PCI_PAR : Out std_logic;
- PCI_PERRn : Out std_logic;
- PCI_SERRn : Out std_logic;
- PERR : Out std_logic;
- SERR : Out std_logic );
- end component;
+ component PARITY_OUT
+ Port ( OE_PCI_PAR : In std_logic;
+ OE_PCI_PERR : In std_logic;
+ PA_ER_RE : In std_logic;
+ PAR_IN : In std_logic_vector (2 downto 0);
+ PAR_REG : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_PAR_IN : In std_logic;
+ PCI_RSTn : In std_logic;
+ PERR_CHECK : In std_logic;
+ SERR_CHECK : In std_logic;
+ SERR_ENA : In std_logic;
+ PCI_PAR : Out std_logic;
+ PCI_PERRn : Out std_logic;
+ PCI_SERRn : Out std_logic;
+ PERR : Out std_logic;
+ SERR : Out std_logic );
+ end component;
- component PARITY_4
- Port ( PAR_IN : In std_logic_vector (3 downto 0);
- PAR_OUT : Out std_logic );
- end component;
+ component PARITY_4
+ Port ( PAR_IN : In std_logic_vector (3 downto 0);
+ PAR_OUT : Out std_logic );
+ end component;
begin
- I12 : PARITY_OUT
- Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,
- PA_ER_RE=>PA_ER_RE,
- PAR_IN(2 downto 0)=>PAR_OUT(10 downto 8),
- PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,
- PCI_PAR_IN=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
- PERR_CHECK=>PERR_CHECK, SERR_CHECK=>SERR_CHECK,
- SERR_ENA=>SERR_ENA, PCI_PAR=>PCI_PAR,
- PCI_PERRn=>PCI_PERRn, PCI_SERRn=>PCI_SERRn, PERR=>PERR,
- SERR=>SERR );
- I9 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_IN(35 downto 32),
- PAR_OUT=>PAR_OUT(8) );
- I11 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(7 downto 4),
- PAR_OUT=>PAR_OUT(10) );
- I8 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_IN(31 downto 28),
- PAR_OUT=>PAR_OUT(7) );
- I7 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_IN(27 downto 24),
- PAR_OUT=>PAR_OUT(6) );
- I6 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_IN(23 downto 20),
- PAR_OUT=>PAR_OUT(5) );
- I5 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_IN(19 downto 16),
- PAR_OUT=>PAR_OUT(4) );
- I4 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_IN(15 downto 12),
- PAR_OUT=>PAR_OUT(3) );
- I3 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_IN(11 downto 8),
- PAR_OUT=>PAR_OUT(2) );
- I2 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_IN(7 downto 4),
- PAR_OUT=>PAR_OUT(1) );
- I1 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_IN(3 downto 0),
- PAR_OUT=>PAR_OUT(0) );
- I10 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(3 downto 0),
- PAR_OUT=>PAR_OUT(9) );
+ I12 : PARITY_OUT
+ Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,
+ PA_ER_RE=>PA_ER_RE,
+ PAR_IN(2 downto 0)=>PAR_OUT(10 downto 8),
+ PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,
+ PCI_PAR_IN=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
+ PERR_CHECK=>PERR_CHECK, SERR_CHECK=>SERR_CHECK,
+ SERR_ENA=>SERR_ENA, PCI_PAR=>PCI_PAR,
+ PCI_PERRn=>PCI_PERRn, PCI_SERRn=>PCI_SERRn, PERR=>PERR,
+ SERR=>SERR );
+ I9 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_IN(35 downto 32),
+ PAR_OUT=>PAR_OUT(8) );
+ I11 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(7 downto 4),
+ PAR_OUT=>PAR_OUT(10) );
+ I8 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_IN(31 downto 28),
+ PAR_OUT=>PAR_OUT(7) );
+ I7 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_IN(27 downto 24),
+ PAR_OUT=>PAR_OUT(6) );
+ I6 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_IN(23 downto 20),
+ PAR_OUT=>PAR_OUT(5) );
+ I5 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_IN(19 downto 16),
+ PAR_OUT=>PAR_OUT(4) );
+ I4 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_IN(15 downto 12),
+ PAR_OUT=>PAR_OUT(3) );
+ I3 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_IN(11 downto 8),
+ PAR_OUT=>PAR_OUT(2) );
+ I2 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_IN(7 downto 4),
+ PAR_OUT=>PAR_OUT(1) );
+ I1 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_IN(3 downto 0),
+ PAR_OUT=>PAR_OUT(0) );
+ I10 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(3 downto 0),
+ PAR_OUT=>PAR_OUT(9) );
end SCHEMATIC;