- I19 : USER_IO
- Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
- ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
- CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
- FLAG(7 downto 0)=>FLAG(7 downto 0),
- INT_REG(7 downto 0)=>INT_REG(7 downto 0),
- IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
- PCI_CLK=>PCI_CLOCK,
- R_FIFO_Q(7 downto 0)=>R_FIFO_Q(7 downto 0),
- READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
- TRDYn=>TRDYn_DUMMY, READ_XX1_0=>READ_XX1_0,
- READ_XX3_2=>READ_XX3_2_DUMMY, READ_XX5_4=>READ_XX5_4,
- READ_XX7_6=>READ_XX7_6,
- REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0(7 downto 0),
- REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
- REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
- USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
- WRITE_XX1_0=>WRITE_XX1_0, WRITE_XX3_2=>WRITE_XX3_2,
- WRITE_XX5_4=>WRITE_XX5_4, WRITE_XX7_6=>WRITE_XX7_6 );
- I10 : PCI_INTERFACE
- Port Map ( PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
- PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
- PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
- PCI_RSTn=>PCI_RSTn, READ_FIFO=>READ_XX3_2_DUMMY,
- REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
- USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
- VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
- PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
- PCI_PAR=>PCI_PAR,
- AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
- ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
- CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
- DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
- IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
- PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,
- PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,
- PCI_TRDYn=>PCI_TRDYn,
- READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
- TRDYn=>TRDYn_DUMMY );
+ I19 : USER_IO
+ Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+ ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+ CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+ FLAG(7 downto 0)=>FLAG(7 downto 0),
+ INT_REG(7 downto 0)=>INT_REG(7 downto 0),
+ IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
+ PCI_CLK=>PCI_CLOCK,
+ R_FIFO_Q(7 downto 0)=>R_FIFO_Q(7 downto 0),
+ READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
+ TRDYn=>TRDYn_DUMMY, READ_XX1_0=>READ_XX1_0,
+ READ_XX3_2=>READ_XX3_2_DUMMY, READ_XX5_4=>READ_XX5_4,
+ READ_XX7_6=>READ_XX7_6,
+ REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0(7 downto 0),
+ REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
+ REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
+ USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
+ WRITE_XX1_0=>WRITE_XX1_0, WRITE_XX3_2=>WRITE_XX3_2,
+ WRITE_XX5_4=>WRITE_XX5_4, WRITE_XX7_6=>WRITE_XX7_6 );
+ I10 : PCI_INTERFACE
+ Port Map ( PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
+ PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
+ PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
+ PCI_RSTn=>PCI_RSTn, READ_FIFO=>READ_XX3_2_DUMMY,
+ REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
+ USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
+ VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
+ PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
+ PCI_PAR=>PCI_PAR,
+ AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+ ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+ CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+ DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
+ IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
+ PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,
+ PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,
+ PCI_TRDYn=>PCI_TRDYn,
+ READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
+ TRDYn=>TRDYn_DUMMY );