- REG_OUT_XX0 <= REG_OUT_XX0_DUMMY;
- REG_OUT_XX6 <= REG_OUT_XX6_DUMMY;
- REG_OUT_XX7 <= REG_OUT_XX7_DUMMY;
- WRITE_XX7_6 <= WRITE_XX7_6_DUMMY;
- WRITE_XX1_0 <= WRITE_XX1_0_DUMMY;
-
- I4 : IO_WR_SEL
- Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
- CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
- IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
- TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0_DUMMY,
- WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
- WRITE_XX7_6=>WRITE_XX7_6_DUMMY );
- I2 : DATA_MUX
- Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
- CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
- MUX_IN_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),
- MUX_IN_XX1(7 downto 0)=>FLAG(7 downto 0),
- MUX_IN_XX2(7 downto 0)=>R_FIFO_Q(7 downto 0),
- MUX_IN_XX3(7 downto 0)=>FLAG(7 downto 0),
- MUX_IN_XX4(7 downto 0)=>INT_REG(7 downto 0),
- MUX_IN_XX5(7 downto 0)=>FLAG(7 downto 0),
- MUX_IN_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),
- MUX_IN_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0),
- READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
- MUX_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
- READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
- READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6 );
- I1 : REG_IO
- Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
- PCI_CLOCK=>PCI_CLK, RESET=>REG_OUT_XX7_DUMMY(0),
- WRITE_XX1_0=>WRITE_XX1_0_DUMMY,
- WRITE_XX7_6=>WRITE_XX7_6_DUMMY,
- REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),
- REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),
- REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0) );
+ REG_OUT_XX0 <= REG_OUT_XX0_DUMMY;
+ REG_OUT_XX6 <= REG_OUT_XX6_DUMMY;
+ REG_OUT_XX7 <= REG_OUT_XX7_DUMMY;
+ WRITE_XX7_6 <= WRITE_XX7_6_DUMMY;
+ WRITE_XX1_0 <= WRITE_XX1_0_DUMMY;
+
+ I4 : IO_WR_SEL
+ Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+ CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+ IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
+ TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0_DUMMY,
+ WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
+ WRITE_XX7_6=>WRITE_XX7_6_DUMMY );
+ I2 : DATA_MUX
+ Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+ CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+ MUX_IN_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),
+ MUX_IN_XX1(7 downto 0)=>FLAG(7 downto 0),
+ MUX_IN_XX2(7 downto 0)=>R_FIFO_Q(7 downto 0),
+ MUX_IN_XX3(7 downto 0)=>FLAG(7 downto 0),
+ MUX_IN_XX4(7 downto 0)=>INT_REG(7 downto 0),
+ MUX_IN_XX5(7 downto 0)=>FLAG(7 downto 0),
+ MUX_IN_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),
+ MUX_IN_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0),
+ READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
+ MUX_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
+ READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
+ READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6 );
+ I1 : REG_IO
+ Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+ PCI_CLOCK=>PCI_CLK, RESET=>REG_OUT_XX7_DUMMY(0),
+ WRITE_XX1_0=>WRITE_XX1_0_DUMMY,
+ WRITE_XX7_6=>WRITE_XX7_6_DUMMY,
+ REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),
+ REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),
+ REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0) );