-library ieee ;
-use ieee.std_logic_1164.all ;
-
-entity VERG_2 is
- port
- (
- IN_A :in std_logic_vector(1 downto 0);
- IN_B :in std_logic_vector(1 downto 0);
- GLEICH :out std_logic
- );
-end entity VERG_2 ;
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity VERG_2 is
+ port
+ (
+ IN_A :in std_logic_vector(1 downto 0);
+ IN_B :in std_logic_vector(1 downto 0);
+ GLEICH :out std_logic
+ );
+end entity VERG_2;