- SIGNAL gnd : std_logic := '0';
- SIGNAL vcc : std_logic := '1';
-
- signal IRDY_REGn_DUMMY : std_logic;
- signal PAR_REG : std_logic;
- signal PERR : std_logic;
- signal SERR : std_logic;
- signal CF_RD_COM : std_logic;
- signal CF_WR_COM : std_logic;
- signal LAR : std_logic;
- signal MY_ADDR : std_logic;
- signal SERR_CHECK : std_logic;
- signal IDSEL_REG : std_logic;
- signal FRAME_REGn : std_logic;
- signal PERR_CHECK : std_logic;
- signal OE_PCI_PAR : std_logic;
- signal OE_PCI_PERR : std_logic;
- signal TRDYn_DUMMY : std_logic;
- signal CONF_DATA_10H : std_logic_vector (31 downto 0);
- signal CONF_DATA_04H : std_logic_vector (31 downto 0);
- signal CONF_DATA : std_logic_vector (31 downto 0);
- signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);
- signal CBE_REGn_DUMMY : std_logic_vector (3 downto 0);
- signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
- signal ADDR_REG_DUMMY : std_logic_vector (31 downto 0);
-
- component STEUERUNG
- Port ( AD_REG : In std_logic_vector (31 downto 0);
- CBE_REGn : In std_logic_vector (3 downto 0);
- FRAME_REGn : In std_logic;
- IDSEL_REG : In std_logic;
- IO_SPACE : In std_logic;
- MY_ADDR : In std_logic;
- PCI_CLOCK : In std_logic;
- PCI_RSTn : In std_logic;
- READ_FIFO : In std_logic;
- CF_RD_COM : Out std_logic;
- CF_WR_COM : Out std_logic;
- DEVSELn : Out std_logic;
- FIFO_RDn : Out std_logic;
- IO_RD_COM : Out std_logic;
- IO_WR_COM : Out std_logic;
- LAR : Out std_logic;
- OE_PCI_PAR : Out std_logic;
- OE_PCI_PERR : Out std_logic;
- PCI_DEVSELn : Out std_logic;
- PCI_STOPn : Out std_logic;
- PCI_TRDYn : Out std_logic;
- PERR_CHECK : Out std_logic;
- READ : Out std_logic;
- SERR_CHECK : Out std_logic;
- TRDYn : Out std_logic );
- end component;
-
- component PARITY
- Port ( OE_PCI_PAR : In std_logic;
- OE_PCI_PERR : In std_logic;
- PA_ER_RE : In std_logic;
- PAR_IN : In std_logic_vector (35 downto 0);
- PAR_REG : In std_logic;
- PCI_CLOCK : In std_logic;
- PCI_RSTn : In std_logic;
- PERR_CHECK : In std_logic;
- SERR_CHECK : In std_logic;
- SERR_ENA : In std_logic;
- PCI_PAR : InOut std_logic;
- PCI_PERRn : Out std_logic;
- PCI_SERRn : Out std_logic;
- PERR : Out std_logic;
- SERR : Out std_logic );
- end component;
-
- component VERGLEICH
- Port ( IN_A : In std_logic_vector (31 downto 0);
- IN_B : In std_logic_vector (31 downto 0);
- GLEICH_OUT : Out std_logic );
- end component;
-
- component IO_MUX_REG
- Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
- LOAD_ADDR_REG : In std_logic;
- PCI_CBEn : In std_logic_vector (3 downto 0);
- PCI_CLOCK : In std_logic;
- PCI_FRAMEn : In std_logic;
- PCI_IDSEL : In std_logic;
- PCI_IRDYn : In std_logic;
- PCI_PAR : In std_logic;
- PCI_RSTn : In std_logic;
- READ_SEL : In std_logic_vector (1 downto 0);
- USER_DATA : In std_logic_vector (31 downto 0);
- PCI_AD : InOut std_logic_vector (31 downto 0);
- AD_REG : Out std_logic_vector (31 downto 0);
- ADDR_REG : Out std_logic_vector (31 downto 0);
- CBE_REGn : Out std_logic_vector (3 downto 0);
- FRAME_REGn : Out std_logic;
- IDSEL_REG : Out std_logic;
- IRDY_REGn : Out std_logic;
- PAR_REG : Out std_logic );
- end component;
-
- component CONFIG_SPACE_HEADER
- Port ( AD_REG : In std_logic_vector (31 downto 0);
- ADDR_REG : In std_logic_vector (31 downto 0);
- CBE_REGn : In std_logic_vector (3 downto 0);
- CF_RD_COM : In std_logic;
- CF_WR_COM : In std_logic;
- IRDY_REGn : In std_logic;
- PCI_CLOCK : In std_logic;
- PCI_RSTn : In std_logic;
- PERR : In std_logic;
- REVISION_ID : In std_logic_vector (7 downto 0);
- SERR : In std_logic;
- TRDYn : In std_logic;
- VENDOR_ID : In std_logic_vector (15 downto 0);
- CONF_DATA : Out std_logic_vector (31 downto 0);
- CONF_DATA_04H : Out std_logic_vector (31 downto 0);
- CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
- end component;
+ SIGNAL gnd : std_logic := '0';
+ SIGNAL vcc : std_logic := '1';
+
+ signal IRDY_REGn_DUMMY : std_logic;
+ signal PAR_REG : std_logic;
+ signal PERR : std_logic;
+ signal SERR : std_logic;
+ signal CF_RD_COM : std_logic;
+ signal CF_WR_COM : std_logic;
+ signal LAR : std_logic;
+ signal MY_ADDR : std_logic;
+ signal SERR_CHECK : std_logic;
+ signal IDSEL_REG : std_logic;
+ signal FRAME_REGn : std_logic;
+ signal PERR_CHECK : std_logic;
+ signal OE_PCI_PAR : std_logic;
+ signal OE_PCI_PERR : std_logic;
+ signal TRDYn_DUMMY : std_logic;
+ signal CONF_DATA_10H : std_logic_vector (31 downto 0);
+ signal CONF_DATA_04H : std_logic_vector (31 downto 0);
+ signal CONF_DATA : std_logic_vector (31 downto 0);
+ signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);
+ signal CBE_REGn_DUMMY : std_logic_vector (3 downto 0);
+ signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
+ signal ADDR_REG_DUMMY : std_logic_vector (31 downto 0);
+
+ component STEUERUNG
+ Port ( AD_REG : In std_logic_vector (31 downto 0);
+ CBE_REGn : In std_logic_vector (3 downto 0);
+ FRAME_REGn : In std_logic;
+ IDSEL_REG : In std_logic;
+ IO_SPACE : In std_logic;
+ MY_ADDR : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ READ_FIFO : In std_logic;
+ CF_RD_COM : Out std_logic;
+ CF_WR_COM : Out std_logic;
+ DEVSELn : Out std_logic;
+ FIFO_RDn : Out std_logic;
+ IO_RD_COM : Out std_logic;
+ IO_WR_COM : Out std_logic;
+ LAR : Out std_logic;
+ OE_PCI_PAR : Out std_logic;
+ OE_PCI_PERR : Out std_logic;
+ PCI_DEVSELn : Out std_logic;
+ PCI_STOPn : Out std_logic;
+ PCI_TRDYn : Out std_logic;
+ PERR_CHECK : Out std_logic;
+ READ : Out std_logic;
+ SERR_CHECK : Out std_logic;
+ TRDYn : Out std_logic );
+ end component;
+
+ component PARITY
+ Port ( OE_PCI_PAR : In std_logic;
+ OE_PCI_PERR : In std_logic;
+ PA_ER_RE : In std_logic;
+ PAR_IN : In std_logic_vector (35 downto 0);
+ PAR_REG : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ PERR_CHECK : In std_logic;
+ SERR_CHECK : In std_logic;
+ SERR_ENA : In std_logic;
+ PCI_PAR : InOut std_logic;
+ PCI_PERRn : Out std_logic;
+ PCI_SERRn : Out std_logic;
+ PERR : Out std_logic;
+ SERR : Out std_logic );
+ end component;
+
+ component VERGLEICH
+ Port ( IN_A : In std_logic_vector (31 downto 0);
+ IN_B : In std_logic_vector (31 downto 0);
+ GLEICH_OUT : Out std_logic );
+ end component;
+
+ component IO_MUX_REG
+ Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
+ LOAD_ADDR_REG : In std_logic;
+ PCI_CBEn : In std_logic_vector (3 downto 0);
+ PCI_CLOCK : In std_logic;
+ PCI_FRAMEn : In std_logic;
+ PCI_IDSEL : In std_logic;
+ PCI_IRDYn : In std_logic;
+ PCI_PAR : In std_logic;
+ PCI_RSTn : In std_logic;
+ READ_SEL : In std_logic_vector (1 downto 0);
+ USER_DATA : In std_logic_vector (31 downto 0);
+ PCI_AD : InOut std_logic_vector (31 downto 0);
+ AD_REG : Out std_logic_vector (31 downto 0);
+ ADDR_REG : Out std_logic_vector (31 downto 0);
+ CBE_REGn : Out std_logic_vector (3 downto 0);
+ FRAME_REGn : Out std_logic;
+ IDSEL_REG : Out std_logic;
+ IRDY_REGn : Out std_logic;
+ PAR_REG : Out std_logic );
+ end component;
+
+ component CONFIG_SPACE_HEADER
+ Port ( AD_REG : In std_logic_vector (31 downto 0);
+ ADDR_REG : In std_logic_vector (31 downto 0);
+ CBE_REGn : In std_logic_vector (3 downto 0);
+ CF_RD_COM : In std_logic;
+ CF_WR_COM : In std_logic;
+ IRDY_REGn : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ PERR : In std_logic;
+ REVISION_ID : In std_logic_vector (7 downto 0);
+ SERR : In std_logic;
+ TRDYn : In std_logic;
+ VENDOR_ID : In std_logic_vector (15 downto 0);
+ CONF_DATA : Out std_logic_vector (31 downto 0);
+ CONF_DATA_04H : Out std_logic_vector (31 downto 0);
+ CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
+ end component;