enable address translation

[raggedstone] / ethernet / source / top.vhd

diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd
index d181c526bad9c216cbb6ff03020f51cd437daf32..34d0bdc6c558530e9aaa99e49ad046dbcdf63724 100644 (file)
--- a/ethernet/source/top.vhd
+++ b/ethernet/source/top.vhd
@@ -154,48 +154,20 @@ PORT(
         );
 END COMPONENT;
 
         );
 END COMPONENT;
 

-COMPONENT eth_cop
-PORT(
-       wb_clk_i : IN std_logic;
-       wb_rst_i : IN std_logic;
-       m1_wb_adr_i : IN std_logic_vector(31 downto 0);
-       m1_wb_sel_i : IN std_logic_vector(3 downto 0);
-       m1_wb_we_i : IN std_logic;
-       m1_wb_dat_i : IN std_logic_vector(31 downto 0);
-       m1_wb_cyc_i : IN std_logic;
-       m1_wb_stb_i : IN std_logic;
-       m2_wb_adr_i : IN std_logic_vector(31 downto 0);
-       m2_wb_sel_i : IN std_logic_vector(3 downto 0);
-       m2_wb_we_i : IN std_logic;
-       m2_wb_dat_i : IN std_logic_vector(31 downto 0);
-       m2_wb_cyc_i : IN std_logic;
-       m2_wb_stb_i : IN std_logic;
-       s1_wb_ack_i : IN std_logic;
-       s1_wb_err_i : IN std_logic;
-       s1_wb_dat_i : IN std_logic_vector(31 downto 0);
-       s2_wb_ack_i : IN std_logic;
-       s2_wb_err_i : IN std_logic;
-       s2_wb_dat_i : IN std_logic_vector(31 downto 0);          
-       m1_wb_dat_o : OUT std_logic_vector(31 downto 0);
-       m1_wb_ack_o : OUT std_logic;
-       m1_wb_err_o : OUT std_logic;
-       m2_wb_dat_o : OUT std_logic_vector(31 downto 0);
-       m2_wb_ack_o : OUT std_logic;
-       m2_wb_err_o : OUT std_logic;
-       s1_wb_adr_o : OUT std_logic_vector(31 downto 0);
-       s1_wb_sel_o : OUT std_logic_vector(3 downto 0);
-       s1_wb_we_o : OUT std_logic;
-       s1_wb_cyc_o : OUT std_logic;
-       s1_wb_stb_o : OUT std_logic;
-       s1_wb_dat_o : OUT std_logic_vector(31 downto 0);
-       s2_wb_adr_o : OUT std_logic_vector(31 downto 0);
-       s2_wb_sel_o : OUT std_logic_vector(3 downto 0);
-       s2_wb_we_o : OUT std_logic;
-       s2_wb_cyc_o : OUT std_logic;
-       s2_wb_stb_o : OUT std_logic;
-       s2_wb_dat_o : OUT std_logic_vector(31 downto 0)
+component icon
+port (
+       control0 : out std_logic_vector(35 downto 0)

        );
        );

-END COMPONENT;
+end component;
+
+component ila
+port (
+       control : in std_logic_vector(35 downto 0);
+       clk : in std_logic;
+       data : in std_logic_vector(63 downto 0);
+       trig0 : in std_logic_vector(31 downto 0)
+       );
+end component;

 
 signal pci_rst_o : std_logic;
 signal pci_rst_oe_o : std_logic;
 
 signal pci_rst_o : std_logic;
 signal pci_rst_oe_o : std_logic;


@@ -252,6 +224,11 @@ signal wbm_adr_o : std_logic_vector(31 downto 0);
 signal m_wb_cti_o : std_logic_vector(2 downto 0);
 signal m_wb_bte_o : std_logic_vector(1 downto 0);
 
 signal m_wb_cti_o : std_logic_vector(2 downto 0);
 signal m_wb_bte_o : std_logic_vector(1 downto 0);
 

+signal control0 : std_logic_vector(35 downto 0);
+signal data : std_logic_vector(63 downto 0);
+signal trig0 : std_logic_vector(31 downto 0);
+
+

 BEGIN
 
 PCI_RSTn    <= pci_rst_o    when (pci_rst_oe_o = '1')     else 'Z';
 BEGIN
 
 PCI_RSTn    <= pci_rst_o    when (pci_rst_oe_o = '1')     else 'Z';


@@ -277,6 +254,16 @@ end generate;
 
 wb_adr_i <= wbm_adr_o (11 downto 2);
 
 
 wb_adr_i <= wbm_adr_o (11 downto 2);
 

+wb_clk_i <= PCI_CLOCK;
+
+data(31 downto 0) <= wbm_adr_o;
+data(63 downto 32) <= (others => '0');
+
+trig0(31 downto 0) <= (
+       0 => wb_stb_i,
+       others => '0'
+);
+

 Inst_pci_bridge32: pci_bridge32 PORT MAP(
         wb_clk_i => wb_clk_i ,
         wb_rst_i => '0',
 Inst_pci_bridge32: pci_bridge32 PORT MAP(
         wb_clk_i => wb_clk_i ,
         wb_rst_i => '0',


@@ -389,45 +376,17 @@ Inst_eth_top: eth_top PORT MAP(
         int_o => int_o
 );
 
         int_o => int_o
 );
 

---Inst_eth_cop: eth_cop PORT MAP(
---     wb_clk_i => ,
---     wb_rst_i => ,
---     m1_wb_adr_i => ,
---     m1_wb_sel_i => ,
---     m1_wb_we_i => ,
---     m1_wb_dat_o => ,
---     m1_wb_dat_i => ,
---     m1_wb_cyc_i => ,
---     m1_wb_stb_i => ,
---     m1_wb_ack_o => ,
---     m1_wb_err_o => ,
---     m2_wb_adr_i => ,
---     m2_wb_sel_i => ,
---     m2_wb_we_i => ,
---     m2_wb_dat_o => ,
---     m2_wb_dat_i => ,
---     m2_wb_cyc_i => ,
---     m2_wb_stb_i => ,
---     m2_wb_ack_o => ,
---     m2_wb_err_o => ,
---     s1_wb_adr_o => ,
---     s1_wb_sel_o => ,
---     s1_wb_we_o => ,
---     s1_wb_cyc_o => ,
---     s1_wb_stb_o => ,
---     s1_wb_ack_i => ,
---     s1_wb_err_i => ,
---     s1_wb_dat_i => ,
---     s1_wb_dat_o => ,
---     s2_wb_adr_o => ,
---     s2_wb_sel_o => ,
---     s2_wb_we_o => ,
---     s2_wb_cyc_o => ,
---     s2_wb_stb_o => ,
---     s2_wb_ack_i => ,
---     s2_wb_err_i => ,
---     s2_wb_dat_i => ,
---     s2_wb_dat_o => 
---);
+i_icon : icon
+port map (
+       control0 => control0
+       );
+
+i_ila : ila
+port map (
+       control => control0,
+       clk => PCI_CLOCK,
+       data => data,
+       trig0 => trig0
+       );

 
 end architecture ethernet_arch;
 
 end architecture ethernet_arch;