-module wb_7seg_new (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i, \r
+module wb_fifo (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i, \r
wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, fifo_data_i, fifo_data_o, fifo_we_o, fifo_re_o);\r
\r
input clk_i;\r
output fifo_we_o;\r
output fifo_re_o;\r
\r
- reg [15:0] data_reg;\r
+ reg [15:0] data_reg;\r
\r
always @(posedge clk_i or negedge nrst_i)\r
begin\r
if (nrst_i == 0)\r
- data_reg <= 16'hABCD;\r
+ data_reg <= 16'h0000;\r
else \r
- if (wb_stb_i && wb_we_i)\r
- data_reg <= wb_dat_i;\r
+ if (wb_stb_i && wb_we_i)\r
+ data_reg <= wb_dat_i;\r
end\r
\r
+ assign fifo_we_o = 1'b1;\r
+ assign fifo_data_o = data_reg;\r
+\r
assign wb_ack_o = wb_stb_i;\r
assign wb_err_o = 1'b0;\r
assign wb_int_o = 1'b0;\r