code cleanup

[raggedstone] / dhwk / source / INTERRUPT.vhd

diff --git a/dhwk/source/INTERRUPT.vhd b/dhwk/source/INTERRUPT.vhd
index d4b8b45ff92681a8b3ced4e2f2dcf6ed67addd14..cba393572b11e86209eef3a04c5a51d9fc0ffe94 100644 (file)
--- a/dhwk/source/INTERRUPT.vhd
+++ b/dhwk/source/INTERRUPT.vhd
@@ -59,8 +59,8 @@ begin
        begin \r
                if  (PCI_CLOCK'event and PCI_CLOCK ='1')  then  \r
 \r
        begin \r
                if  (PCI_CLOCK'event and PCI_CLOCK ='1')  then  \r
 \r

+                        -- THIS IS BROKEN (it cycles the interrupt)\r

                        SIG_TAST_Q              <= not (TAST_SETn and SIG_TAST_Qn);\r
                        SIG_TAST_Q              <= not (TAST_SETn and SIG_TAST_Qn);\r

-                       \r

                        SIG_TAST_Qn             <= not (TAST_RESn and SIG_TAST_Q);\r
        \r
                end if;\r
                        SIG_TAST_Qn             <= not (TAST_RESn and SIG_TAST_Q);\r
        \r
                end if;\r


@@ -110,8 +110,9 @@ begin
                                if(RESET = '1') then\r
                                        REG <= "00000000";\r
 \r
                                if(RESET = '1') then\r
                                        REG <= "00000000";\r
 \r

-               elsif(SIG_TAST_Q = '1') then\r
-                       REG <= "00000000" or SET;\r
+               -- elsif(SIG_TAST_Q = '1') then\r
+               --      REG <= "00000000" or SET;\r
+               \r

 \r
         elsif (TRDYn = '0' AND READ_XX5_4 = '1') then\r
             REG <= (REG AND NOT INT_RES) OR SET;\r
 \r
         elsif (TRDYn = '0' AND READ_XX5_4 = '1') then\r
             REG <= (REG AND NOT INT_RES) OR SET;\r


@@ -121,8 +122,8 @@ begin
     end if;\r
        end process;\r
 \r
     end if;\r
        end process;\r
 \r

-       SIG_PROPAGATE_INT <= SIG_TAST_Q\r
-            OR (REG(0) AND INT_MASKE(0)) \r
+       SIG_PROPAGATE_INT <=\r
+            (REG(0) AND INT_MASKE(0)) \r

             OR (REG(1) AND INT_MASKE(1))\r
             OR (REG(2) AND INT_MASKE(2))\r
             OR (REG(3) AND INT_MASKE(3))\r
             OR (REG(1) AND INT_MASKE(1))\r
             OR (REG(2) AND INT_MASKE(2))\r
             OR (REG(3) AND INT_MASKE(3))\r