port (
clk_i : in std_logic;
nrst_i : in std_logic;
- led_o : out std_logic
+ led2_o : out std_logic;
+ led3_o : out std_logic;
+ led4_o : out std_logic;
+ led5_o : out std_logic
);
end heartbeat;
if nrst_i = '0' then
counter := (others => '0');
else
- led_o <= state;
+ led5_o <= state;
+ led2_o <= state;
+ led4_o <= not state;
+ led3_o <= not state;
counter := counter + 1;
if counter = divider then
state := not state;