PCI_nSERR : out std_logic;\r
PCI_nINT : out std_logic;\r
\r
- -- 7seg\r
- DISP_SEL : inout std_logic_vector(3 downto 0);\r
- DISP_LED : out std_logic_vector(6 downto 0);\r
- \r
-- debug signals\r
LED_INIT : out std_logic;\r
LED_ACCESS : out std_logic;\r
- LED_ALIVE : out std_logic;\r
-\r
- -- vga signals\r
- hs : out std_logic;\r
- vs : out std_logic;\r
- red, grn, blu : out std_logic;\r
- mclk : in std_logic\r
+ LED_ALIVE : out std_logic\r
\r
);\r
end pci_7seg;\r
);\r
end component;\r
\r
-\r
-component wb_7seg_new\r
+component heartbeat\r
port (\r
- \r
- -- General \r
- clk_i : in std_logic;\r
- nrst_i : in std_logic;\r
- \r
- -- Master whisbone\r
- wb_adr_i : in std_logic_vector(24 downto 1); \r
- wb_dat_o : out std_logic_vector(15 downto 0);\r
- wb_dat_i : in std_logic_vector(15 downto 0);\r
- wb_sel_i : in std_logic_vector(1 downto 0);\r
- wb_we_i : in std_logic;\r
- wb_stb_i : in std_logic;\r
- wb_cyc_i : in std_logic;\r
- wb_ack_o : out std_logic;\r
- wb_err_o : out std_logic;\r
- wb_int_o : out std_logic;\r
-\r
- -- 7seg\r
- DISP_SEL : inout std_logic_vector(3 downto 0);\r
- DISP_LED : out std_logic_vector(6 downto 0)\r
-\r
- );\r
-end component;\r
-\r
-\r
-component vgaController is\r
- Port ( mclk : in std_logic;\r
- hs : out std_logic;\r
- vs : out std_logic;\r
- red : out std_logic;\r
- grn : out std_logic;\r
- blu : out std_logic);\r
+ clk_i : in std_logic;\r
+ nrst_i : in std_logic;\r
+ led_o : out std_logic\r
+);\r
end component;\r
\r
\r
\r
begin\r
\r
- LED_ALIVE <= '1';\r
---+-------------------------------------------------------------------------+\r
---| Component instances |\r
---+-------------------------------------------------------------------------+\r
-\r
- vga1: vgaController port map (mclk => mclk,\r
- hs => hs,\r
- vs => vs,\r
- red => red,\r
- grn => grn,\r
- blu => blu);\r
-\r
--+-----------------------------------------+\r
--| PCI Target |\r
--+-----------------------------------------+\r
--| WB-7seg |\r
--+-----------------------------------------+\r
\r
-u_wb: component wb_7seg_new\r
-port map(\r
- clk_i => PCI_CLK,\r
- nrst_i => PCI_nRES,\r
- wb_adr_i => wb_adr, \r
- wb_dat_o => wb_dat_out,\r
- wb_dat_i => wb_dat_in,\r
- wb_sel_i => wb_sel,\r
- wb_we_i => wb_we,\r
- wb_stb_i => wb_stb,\r
- wb_cyc_i => wb_cyc,\r
- wb_ack_o => wb_ack,\r
- wb_err_o => wb_err,\r
- wb_int_o => wb_int,\r
- DISP_SEL => DISP_SEL,\r
- DISP_LED => DISP_LED\r
+my_heartbeat: component heartbeat\r
+port map( \r
+ clk_i => PCI_CLK,\r
+ nrst_i => PCI_nRES,\r
+ led_o => LED_ALIVE\r
);\r
\r
end pci_7seg_arch;\r