WRITE_XX7_6 : Out std_logic );\r
end component;\r
\r
-component fifo_generator_v3_2\r
+component dhwk_fifo\r
port (\r
clk: IN std_logic;\r
din: IN std_logic_VECTOR(7 downto 0);\r
WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
WRITE_XX7_6=>WRITE_XX7_6 );\r
\r
-receive_fifo : fifo_generator_v3_2\r
+receive_fifo : dhwk_fifo\r
port map (\r
clk => PCI_CLOCK,\r
din => R_FIFO_D_IN,\r
full => R_FFn,\r
prog_full => R_HFn);\r
\r
-send_fifo : fifo_generator_v3_2\r
+send_fifo : dhwk_fifo\r
port map (\r
clk => PCI_CLOCK,\r
din => S_FIFO_D_IN,\r