signal SPC_RDY_OUT : std_logic;\r
signal watch : std_logic;\r
signal control0 : std_logic_vector(35 downto 0);\r
signal SPC_RDY_OUT : std_logic;\r
signal watch : std_logic;\r
signal control0 : std_logic_vector(35 downto 0);\r
SERIAL_OUT : Out std_logic;\r
SPC_RDY_OUT : Out std_logic;\r
SR_ERROR : Out std_logic;\r
SERIAL_OUT : Out std_logic;\r
SPC_RDY_OUT : Out std_logic;\r
SR_ERROR : Out std_logic;\r
data(16) <= SPC_RDY_IN;\r
data(17) <= SERIAL_OUT;\r
data(18) <= SPC_RDY_OUT;\r
data(16) <= SPC_RDY_IN;\r
data(17) <= SERIAL_OUT;\r
data(18) <= SPC_RDY_OUT;\r
+ data(26 downto 19) <= S_FIFO_Q_OUT;\r
+ data(34 downto 27) <= R_FIFO_Q_OUT;\r
+ data(66 downto 35) <= PCI_AD(31 downto 0);\r
+ data(70 downto 67) <= PCI_CBEn(3 downto 0);\r
+ data(71) <= PCI_FRAMEn;\r
\r
I19 : MESS_1_TB\r
Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
\r
I19 : MESS_1_TB\r
Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
I1 : PCI_TOP\r
Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
I1 : PCI_TOP\r
Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
WRITE_XX7_6=>WRITE_XX7_6 );\r
\r
WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
WRITE_XX7_6=>WRITE_XX7_6 );\r
\r