Update ChipScope coregeneration to coregen as used in ISE Design Suite 10.1

[raggedstone] / xps / raggedstone.xmp

diff --git a/xps/raggedstone.xmp b/xps/raggedstone.xmp
index 8b2302fe80de8b64a3d2cfce7d04af33ba37fa86..8e4c715df4e360e97beaaef7706efc26723d70de 100644 (file)
--- a/xps/raggedstone.xmp
+++ b/xps/raggedstone.xmp
@@ -1,6 +1,6 @@
 #Please do not modify this file by hand
-XmpVersion: 9.1.01
-VerMgmt: 9.1.01
+XmpVersion: 9.2.01
+VerMgmt: 9.2.01
 IntStyle: default
 MHS File: raggedstone.mhs
 MSS File: raggedstone.mss
@@ -10,8 +10,8 @@ Device: xc3s1500
 Package: fg456
 SpeedGrade: -4
 UseProjNav: 0
-PNImportBitFile: 
-PNImportBmmFile: 
+PNImportBitFile: projnav/raggedstone.bit
+PNImportBmmFile: implementation/raggedstone_bd.bmm
 UserCmd1: 
 UserCmd1Type: 0
 UserCmd2: 
@@ -26,6 +26,8 @@ SimModel: BEHAVIORAL
 MixLangSim: 1
 UcfFile: data/raggedstone.ucf
 FpgaImpMode: 0
+EnableParTimingError: 0
+EnableResetOptimization: 0
 ShowLicenseDialog: 1
 Processor: microblaze_0
 BootLoop: 0