hack to let the ethernet project build again. timing is broken now...

[raggedstone] / dhwk_old / source / generic_dpram.v

diff --git a/dhwk_old/source/generic_dpram.v b/dhwk_old/source/generic_dpram.v
index d0bd4bf17f2e561debcdf5fd15590a1074471342..e75a91ec25193d529e68c27a0aee66df59cc7c68 100644 (file)
--- a/dhwk_old/source/generic_dpram.v
+++ b/dhwk_old/source/generic_dpram.v
@@ -66,7 +66,13 @@
 // CVS Revision History
 //
 // $Log: generic_dpram.v,v $
-// Revision 1.1  2007-02-11 22:05:26  sithglan
+// Revision 1.3  2007-02-11 22:18:24  michael
+// component for dram
+//
+// Revision 1.2  2007/02/11 22:15:39  sithglan
+// define xilinix and fpga
+//
+// Revision 1.1  2007/02/11 22:05:26  sithglan
 // += dpram
 //
 // Revision 1.4  2002/09/28 08:18:52  rherveille
@@ -102,8 +108,8 @@
 
 //`include "timescale.v"
 
-//`define VENDOR_FPGA
-//`define VENDOR_XILINX
+`define VENDOR_FPGA
+`define VENDOR_XILINX
 //`define VENDOR_ALTERA
 
 module generic_dpram(
@@ -115,8 +121,8 @@ module generic_dpram(
        //
        // Default address and data buses width
        //
-       parameter aw = 5;  // number of bits in address-bus
-       parameter dw = 16; // number of bits in data-bus
+       parameter aw = 12;  // number of bits in address-bus
+       parameter dw = 8; // number of bits in data-bus
 
        //
        // Generic synchronous double-port RAM interface