signal SERIAL_OUT : std_logic;\r
signal SPC_RDY_OUT : std_logic;\r
signal watch : std_logic;\r
+ signal control0 : std_logic_vector(35 downto 0);\r
+ signal data : std_logic_vector(63 downto 0);\r
+ signal trig0 : std_logic_vector(7 downto 0);\r
\r
component MESS_1_TB\r
Port ( DEVSELn : In std_logic;\r
prog_full: OUT std_logic);\r
end component;\r
\r
+component icon\r
+port\r
+ (\r
+ control0 : out std_logic_vector(35 downto 0)\r
+ );\r
+end component;\r
+\r
+ component ila\r
+ port\r
+ (\r
+ control : in std_logic_vector(35 downto 0);\r
+ clk : in std_logic;\r
+ data : in std_logic_vector(63 downto 0);\r
+ trig0 : in std_logic_vector(7 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
begin\r
SERIAL_IN <= SERIAL_OUT;\r
SPC_RDY_IN <= SPC_RDY_OUT;\r
LED_4 <= '0';\r
LED_5 <= not watch;\r
PCI_INTAn <= watch;\r
+ trig0(7 downto 0) <= (others => '0');\r
+ data(31 downto 0) <= PCI_AD(31 downto 0);\r
+ data(32) <= watch;\r
+ \r
+ data(33) <= R_EFn;\r
+ data(34) <= R_HFn;\r
+ data(35) <= R_FFn;\r
+ data(36) <= R_FIFO_READn;\r
+ data(37) <= R_FIFO_RESETn;\r
+ data(38) <= R_FIFO_RTn;\r
+ data(39) <= R_FIFO_WRITEn;\r
+ data(40) <= S_EFn;\r
+ data(41) <= S_HFn;\r
+ data(42) <= S_FFn;\r
+ data(43) <= S_FIFO_READn;\r
+ data(44) <= S_FIFO_RESETn;\r
+ data(45) <= S_FIFO_RTn;\r
+ data(46) <= S_FIFO_WRITEn;\r
+ data(47) <= SERIAL_IN;\r
+ data(48) <= SPC_RDY_IN;\r
+ data(49) <= SERIAL_OUT;\r
+ data(50) <= SPC_RDY_OUT;\r
\r
I19 : MESS_1_TB\r
Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
empty => S_EFn,\r
full => S_FFn,\r
prog_full => S_HFn);\r
+\r
+ i_icon : icon\r
+ port map\r
+ (\r
+ control0 => control0\r
+ );\r
+\r
+ i_ila : ila\r
+ port map\r
+ (\r
+ control => control0,\r
+ clk => PCI_CLOCK,\r
+ data => data,\r
+ trig0 => trig0\r
+ );\r
end SCHEMATIC;\r