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Update ChipScope coregeneration to coregen as used in ISE Design Suite 10.1
[raggedstone]
/
dhwk_old
/
source
/
wb_fifo.v
diff --git
a/dhwk_old/source/wb_fifo.v
b/dhwk_old/source/wb_fifo.v
index 5ffd1b177676d65c33cdd372c5779e7aded5d5cd..8605504e684992f39238927b0f21bed6063639e5 100644
(file)
--- a/
dhwk_old/source/wb_fifo.v
+++ b/
dhwk_old/source/wb_fifo.v
@@
-1,4
+1,4
@@
-module wb_
7seg_new
(clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i,
\r
+module wb_
fifo
(clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i,
\r
wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, fifo_data_i, fifo_data_o, fifo_we_o, fifo_re_o);
\r
\r
input clk_i;
\r
wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, fifo_data_i, fifo_data_o, fifo_we_o, fifo_re_o);
\r
\r
input clk_i;
\r
@@
-13,22
+13,25
@@
module wb_7seg_new (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we
output wb_ack_o;
\r
output wb_err_o;
\r
output wb_int_o;
\r
output wb_ack_o;
\r
output wb_err_o;
\r
output wb_int_o;
\r
- input reg [7:0] fifo_data_i;
\r
- output reg [7:0] fifo_data_o;
\r
- output fifo_we_i;
\r
+ input [7:0] fifo_data_i;
\r
+ output [7:0] fifo_data_o;
\r
output fifo_we_o;
\r
output fifo_we_o;
\r
+ output fifo_re_o;
\r
\r
\r
- reg [15:0]
data_reg;
\r
+ reg [15:0] data_reg;
\r
\r
always @(posedge clk_i or negedge nrst_i)
\r
begin
\r
if (nrst_i == 0)
\r
\r
always @(posedge clk_i or negedge nrst_i)
\r
begin
\r
if (nrst_i == 0)
\r
- data_reg <= 16'h
ABCD
;
\r
+ data_reg <= 16'h
0000
;
\r
else
\r
else
\r
- if (wb_stb_i && wb_we_i)
\r
- data_reg <= wb_dat_i;
\r
+
if (wb_stb_i && wb_we_i)
\r
+
data_reg <= wb_dat_i;
\r
end
\r
\r
end
\r
\r
+ assign fifo_we_o = 1'b1;
\r
+ assign fifo_data_o = data_reg;
\r
+
\r
assign wb_ack_o = wb_stb_i;
\r
assign wb_err_o = 1'b0;
\r
assign wb_int_o = 1'b0;
\r
assign wb_ack_o = wb_stb_i;
\r
assign wb_err_o = 1'b0;
\r
assign wb_int_o = 1'b0;
\r
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