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[raggedstone] / dhwk / source / pci / address_register.vhd

diff --git a/dhwk/source/pci/address_register.vhd b/dhwk/source/pci/address_register.vhd
index 11602a91f14f1b33e83aa80756f669457af34ce6..56c480eb2087d0c92e211c94a3a399764eec05b2 100644 (file)
--- a/dhwk/source/pci/address_register.vhd
+++ b/dhwk/source/pci/address_register.vhd
@@ -1,39 +1,39 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: ADDR_REG.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity ADDRESS_REGISTER is\r
-       port (\r
-                PCI_CLOCK      :in     std_logic;\r
-                PCI_RSTn       :in     std_logic;\r
-                LOAD_ADDR_REG  :in     std_logic;\r
-                AD_REG         :in     std_logic_vector (31 downto 0);\r
-                ADDR_REG       :out    std_logic_vector (31 downto 0)\r
-        );\r
-end entity ADDRESS_REGISTER;\r
-\r
-architecture ADDR_REGI_DESIGN of ADDRESS_REGISTER is\r
-       signal  REG_ADDR        :std_logic_vector (31 downto 0); \r
-begin \r
-\r
-       process (PCI_CLOCK, PCI_RSTn) \r
-       begin\r
-               if      PCI_RSTn = '0'  then\r
-                        REG_ADDR       <= X"00000000";\r
-\r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-                       if LOAD_ADDR_REG = '1' then\r
-                                REG_ADDR       <=      AD_REG;\r
-                       else\r
-                                REG_ADDR       <=      REG_ADDR;\r
-                       end if;\r
-               end if;\r
-       end process;\r
-\r
-       ADDR_REG        <=      REG_ADDR;\r
-\r
-end architecture ADDR_REGI_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: ADDR_REG.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity ADDRESS_REGISTER is
+       port (
+                PCI_CLOCK      :in     std_logic;
+                PCI_RSTn       :in     std_logic;
+                LOAD_ADDR_REG  :in     std_logic;
+                AD_REG         :in     std_logic_vector (31 downto 0);
+                ADDR_REG       :out    std_logic_vector (31 downto 0)
+        );
+end entity ADDRESS_REGISTER;
+
+architecture ADDR_REGI_DESIGN of ADDRESS_REGISTER is
+       signal  REG_ADDR        :std_logic_vector (31 downto 0); 
+begin 
+
+       process (PCI_CLOCK, PCI_RSTn) 
+       begin
+               if      PCI_RSTn = '0'  then
+                        REG_ADDR       <= X"00000000";
+
+               elsif (rising_edge(PCI_CLOCK)) then
+                       if LOAD_ADDR_REG = '1' then
+                                REG_ADDR       <=      AD_REG;
+                       else
+                                REG_ADDR       <=      REG_ADDR;
+                       end if;
+               end if;
+       end process;
+
+       ADDR_REG        <=      REG_ADDR;
+
+end architecture ADDR_REGI_DESIGN;