define xilinix and fpga

[raggedstone] / dhwk_old / source / top_dhwk.vhd

diff --git a/dhwk_old/source/top_dhwk.vhd b/dhwk_old/source/top_dhwk.vhd
index 7c965c1a37194142020d8ba58b457677dc7be145..dbb54e9021612558ff3ab5a72581f03c1399840c 100644 (file)
--- a/dhwk_old/source/top_dhwk.vhd
+++ b/dhwk_old/source/top_dhwk.vhd
@@ -131,6 +131,27 @@ port (
 );\r
 end component;\r
 \r
+component generic_fifo_sc_a\r
+port (\r
+       clk             : in std_logic;\r
+       rst             : in std_logic;\r
+       clr             : in std_logic;\r
+       din             : in std_logic_vector(7 downto 0);\r
+       we              : in std_logic;\r
+       dout            : out std_logic_vector(7 downto 0);\r
+       re              : in std_logic;\r
+       full            : out std_logic;\r
+       full_r          : out std_logic;\r
+       empty           : out std_logic;\r
+       empty_r         : out std_logic;\r
+       full_n          : out std_logic;\r
+       full_n_r        : out std_logic;\r
+       empty_n         : out std_logic;\r
+       empty_n_r       : out std_logic;\r
+       level           : out std_logic_vector(1 downto 0)\r
+);\r
+end component;\r
+\r
 \r
 --+-----------------------------------------------------------------------------+\r
 --|                                                                    CONSTANTS                                                                       |\r