signal SPC_RDY_OUT : std_logic;\r
signal watch : std_logic;\r
signal control0 : std_logic_vector(35 downto 0);\r
signal SPC_RDY_OUT : std_logic;\r
signal watch : std_logic;\r
signal control0 : std_logic_vector(35 downto 0);\r
SERIAL_OUT : Out std_logic;\r
SPC_RDY_OUT : Out std_logic;\r
SR_ERROR : Out std_logic;\r
SERIAL_OUT : Out std_logic;\r
SPC_RDY_OUT : Out std_logic;\r
SR_ERROR : Out std_logic;\r
- trig0(7 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');\r
+ trig0(31 downto 0) <= (\r
+ 0 => watch,\r
+ 1 => R_FIFO_READn,\r
+ 2 => R_FIFO_WRITEn,\r
+ 3 => S_FIFO_READn,\r
+ 4 => S_FIFO_WRITEn, \r
+ 16 => PCI_AD(0),\r
+ 17 => PCI_AD(1),\r
+ 18 => PCI_AD(2),\r
+ 19 => PCI_AD(3),\r
+ 20 => PCI_AD(4),\r
+ 21 => PCI_AD(5),\r
+ 22 => PCI_AD(6),\r
+ 23 => PCI_AD(7),\r
+ 27 => PCI_FRAMEn,\r
+ 28 => PCI_CBEn(0),\r
+ 29 => PCI_CBEn(1),\r
+ 30 => PCI_CBEn(2),\r
+ 31 => PCI_CBEn(3),\r
+ others => '0');\r
+\r
data(16) <= SPC_RDY_IN;\r
data(17) <= SERIAL_OUT;\r
data(18) <= SPC_RDY_OUT;\r
data(16) <= SPC_RDY_IN;\r
data(17) <= SERIAL_OUT;\r
data(18) <= SPC_RDY_OUT;\r
\r
I19 : MESS_1_TB\r
Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
\r
I19 : MESS_1_TB\r
Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
I1 : PCI_TOP\r
Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
I1 : PCI_TOP\r
Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r