--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: VEN_REV_ID.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity VEN_REV_ID is\r
- port\r
- (\r
- VEN_ID :out std_logic_vector(15 downto 0);\r
- REV_ID :out std_logic_vector( 7 downto 0)\r
- );\r
-end entity VEN_REV_ID;\r
-\r
-architecture VEN_REV_ID_DESIGN of VEN_REV_ID is\r
-\r
-begin\r
-\r
- VEN_ID <= X"2222";\r
- REV_ID <= X"01";\r
-\r
-end architecture VEN_REV_ID_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VEN_REV_ID.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity VEN_REV_ID is
+ port
+ (
+ VEN_ID :out std_logic_vector(15 downto 0);
+ REV_ID :out std_logic_vector( 7 downto 0)
+ );
+end entity VEN_REV_ID;
+
+architecture VEN_REV_ID_DESIGN of VEN_REV_ID is
+
+begin
+
+ VEN_ID <= X"2222";
+ REV_ID <= X"01";
+
+end architecture VEN_REV_ID_DESIGN;