more chipscope signals

[raggedstone] / dhwk_old / source / top_dhwk.vhd

diff --git a/dhwk_old/source/top_dhwk.vhd b/dhwk_old/source/top_dhwk.vhd
index 83d7a01a2d6a9d40e077d3fc3d45d81cdf34f62b..13de3520c82ea8c637ed5aee1a07ce78dbab16f2 100644 (file)
--- a/dhwk_old/source/top_dhwk.vhd
+++ b/dhwk_old/source/top_dhwk.vhd
@@ -128,8 +128,8 @@ port (
        fifo_data_i     : in std_logic_vector(7 downto 0);\r
        fifo_data_o     : out std_logic_vector(7 downto 0);\r
 \r
-       fifo_we_out     : out std_logic;\r
-       fifo_re_out     : out std_logic\r
+       fifo_we_o       : out std_logic;\r
+       fifo_re_o       : out std_logic\r
 );\r
 end component;\r
 \r
@@ -187,7 +187,7 @@ my_generic_fifo: component generic_fifo_sc_a
 port map(\r
        clk             => PCI_CLK,\r
        rst             => PCI_nRES,\r
---     clr             =>\r
+       clr             => '0',\r
        din             => fifo_din,\r
        we              => fifo_we,\r
        dout            => fifo_dout,\r
@@ -222,8 +222,8 @@ port map(
        fifo_data_i      => fifo_dout,\r
        fifo_data_o      => fifo_din,\r
 \r
-       fifo_we_out      => fifo_we,\r
-       fifo_re_out      => fifo_re\r
+       fifo_we_o        => fifo_we,\r
+       fifo_re_o        => fifo_re\r
 );\r
 \r
 my_heartbeat: component heartbeat\r