X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/0b6ed0d89260ade25dc0c2dc9fb8aa154fabd6a1..30273618403fd6512926c89f999f97b4722e1709:/dhwk/source/Io_mux.vhd?ds=sidebyside

diff --git a/dhwk/source/Io_mux.vhd b/dhwk/source/Io_mux.vhd
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--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: IO_MUX.VHD
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity IO_MUX is
-        port
-        (
-                READ_SEL :in std_logic_vector ( 1 downto 0);
-                USER_DATA :in std_logic_vector (31 downto 0);
-                CONFIG_DATA :in std_logic_vector (31 downto 0);
-                PCI_AD :in std_logic_vector (31 downto 0);
-                IO_DATA :out std_logic_vector (31 downto 0)
-        );
-end entity IO_MUX;
-
-architecture IO_MUX_DESIGN of IO_MUX is
-
-        signal MUX :std_logic_vector (31 downto 0);
-
-begin
-
-        MUX <= PCI_AD when READ_SEL = "00" else -- WRITE_CONFIG
-               PCI_AD when READ_SEL = "01" else -- WRITE_IO
-               CONFIG_DATA when READ_SEL = "10" else -- READ_CONFIG
-               USER_DATA when READ_SEL = "11" else -- READ_IO
-               CONFIG_DATA;
-
- -- MUX;
-
-        IO_DATA <= MUX;
-
-end architecture IO_MUX_DESIGN;