X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/0b6ed0d89260ade25dc0c2dc9fb8aa154fabd6a1..30273618403fd6512926c89f999f97b4722e1709:/dhwk/source/Verg_2.vhd?ds=inline

diff --git a/dhwk/source/Verg_2.vhd b/dhwk/source/Verg_2.vhd
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--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: VERG_2.VHD
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity VERG_2 is
-        port
-        (
-                IN_A :in std_logic_vector(1 downto 0);
-                IN_B :in std_logic_vector(1 downto 0);
-                GLEICH :out std_logic
-        );
-end entity VERG_2;
-
-architecture VERG_2_DESIGN of VERG_2 is
-
-begin
-
-        process (IN_A,IN_B)
-        begin
-
-        if IN_A = IN_B then
-                GLEICH <= '1';
-        else
-                GLEICH <= '0';
-        end if;
-
-end process;
-
-end architecture VERG_2_DESIGN;