X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/11b038c295a0c1c9a2753ad8cdb6da0480ebc1dc..f69f908ec2b5edbaaa2885a79f6dbe5011462fef:/dhwk/source/pci/fifo_io_control.vhd?ds=sidebyside

diff --git a/dhwk/source/pci/fifo_io_control.vhd b/dhwk/source/pci/fifo_io_control.vhd
index 03f914a..be85395 100644
--- a/dhwk/source/pci/fifo_io_control.vhd
+++ b/dhwk/source/pci/fifo_io_control.vhd
@@ -1,4 +1,4 @@
--- $Id: fifo_io_control.vhd,v 1.3 2007-03-11 12:24:35 sithglan Exp $
+-- $Id: fifo_io_control.vhd,v 1.4 2007-03-11 13:23:11 sithglan Exp $
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -35,7 +35,7 @@ begin
 
         process (PCI_CLOCK)
         begin
-                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if (rising_edge(PCI_CLOCK)) then
                         if (RESET = '1') then
                                 S_FIFO_WRITEn <= '1';
                                 SIG_S_ERROR <= '0';