X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/152884e67f2cea6ff9f5787eab6c72dcffe484e4..a968e3d4ff18fb605ce9ff3af793b4f14982de92:/heartbeat/source/heartbeat.vhd?ds=sidebyside

diff --git a/heartbeat/source/heartbeat.vhd b/heartbeat/source/heartbeat.vhd
index 76f084d..e079bbb 100644
--- a/heartbeat/source/heartbeat.vhd
+++ b/heartbeat/source/heartbeat.vhd
@@ -5,13 +5,16 @@ use ieee.std_logic_unsigned.all;
 
 entity heartbeat is
 generic (
-	divider : integer := 33000000
+	divider : std_logic_vector(31 downto 0) := X"01F78A40"
 );
 
 port (
 	clk_i : in std_logic;
 	nrst_i : in std_logic;
-	led_o : out std_logic
+	led2_o : out std_logic;
+	led3_o : out std_logic;
+	led4_o : out std_logic;
+	led5_o : out std_logic
 );   
 
 end heartbeat;
@@ -28,10 +31,14 @@ if (clk_i'event AND clk_i = '1') then
 	if nrst_i = '0' then
 		counter := (others => '0');
         else
-		led_o <= state;
+		led5_o <= state;
+		led2_o <= state;
+		led4_o <= not state;
+		led3_o <= not state;
 		counter := counter + 1;
 		if counter = divider then
 			state := not state;
+			counter := (others => '0');
 	        end if;
 	end if;
 end if;