X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/30273618403fd6512926c89f999f97b4722e1709..2a7d0ce665689e7d493d3c613e6d02dda135a979:/dhwk/source/pci/fifo_io_control.vhd?ds=sidebyside

diff --git a/dhwk/source/pci/fifo_io_control.vhd b/dhwk/source/pci/fifo_io_control.vhd
index f9faba3..43f3a43 100644
--- a/dhwk/source/pci/fifo_io_control.vhd
+++ b/dhwk/source/pci/fifo_io_control.vhd
@@ -1,4 +1,4 @@
--- $Id: fifo_io_control.vhd,v 1.1 2007-03-11 08:55:29 sithglan Exp $
+-- $Id: fifo_io_control.vhd,v 1.2 2007-03-11 09:14:58 sithglan Exp $
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -35,7 +35,7 @@ begin
 
         process (PCI_CLOCK)
         begin
-                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if (rising_edge(PCI_CLOCK)) then
                         if (RESET = '1') then
                                 S_FIFO_WRITEn <= '1';
                                 SIG_S_ERROR <= '0';