X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/36a53ce255c40f7051820ffbaaac1dd646a83bfb..377c02420489dd18db3ce053a075d7eca4ae799b:/dhwk/source/config_rd_0.vhd

diff --git a/dhwk/source/config_rd_0.vhd b/dhwk/source/config_rd_0.vhd
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+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_RD_0.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_RD_0 is
+    port
+	(
+	ADDR_REG	:in		std_logic_vector (31 downto 0);
+	CF_RD_COM	:in		std_logic;
+	READ_SEL	:out	std_logic_vector ( 2 downto 0)
+    );
+end entity CONFIG_RD_0;
+
+architecture CONFIG_RD_0_DESIGN of CONFIG_RD_0 is
+
+--
+--
+--
+--
+--
+--		               PCI Configuration Space Header
+--
+--            \                        Bit
+--			   \
+--Address		|31		  24|23		  16|15		   8|7		   0|      
+-----------------------------------------------------------------
+--00			|Device ID				|Vendor ID				|					
+--04			|Status					|Command				|
+--08			|Class Code				 			|Revision ID|
+--0C			|BIST		|Header Type|Latency T. |Cache L.S.	|
+--10-24			|Base Address Register							|
+--28			|Cardbus CIS Pointer							|
+--2C			|Subsystem ID			|Subsystem Vendor ID	|
+--30			|Expansion ROM Base Address						|
+--34			|Reserved										|
+--38			|Reserved										|
+--3C			|Max_Lat	|Min_Gnt	|Int_Pin	|Int_Line	|
+--40-FF			|												|
+-----------------------------------------------------------------
+
+
+--PCI Bus Commands 
+--C/BE[3..0] Command Type
+--------------------------------------
+--	0000		Interrupt Acknowledge
+--	0001		Special Cycle
+--	0010		I/O Read
+--	0011		I/O Write
+--	0100		Reserved
+--	0101		Reserved
+--	0110		Memory Read
+--	0111		Memory Write
+--
+--	1000		Reserved
+--	1001		Reserved
+--	1010		Configuration Read
+--	1011		Configuration Write
+--	1100		Memory Read Multiple 
+--	1101		Dual Address Cycle
+--	1110		Memory Read Line
+--	1111		Memory Write and Invalidate
+
+
+--PCI Byte Enable 
+--C/BE[3..0] gueltige Datenbits 
+-------------------------------
+--	0000		AD 31..0
+--	1000		AD 23..0
+--	1100		AD 15..0
+--	1110		AD  7..0
+
+	constant	CMD_INT_ACK			:std_logic_vector(3 downto 0) := "0000";
+	constant	CMD_SP_CYC			:std_logic_vector(3 downto 0) := "0001";
+	constant	CMD_IO_READ			:std_logic_vector(3 downto 0) := "0010";
+	constant	CMD_IO_WRITE		:std_logic_vector(3 downto 0) := "0011";
+	constant	CMD_RES_4				:std_logic_vector(3 downto 0) := "0100";
+	constant	CMD_RES_5				:std_logic_vector(3 downto 0) := "0101";
+	constant	CMD_MEM_READ		:std_logic_vector(3 downto 0) := "0110";
+	constant	CMD_MEM_WRITE		:std_logic_vector(3 downto 0) := "0111";
+	constant	CMD_RES_8				:std_logic_vector(3 downto 0) := "1000";
+	constant	CMD_RES_9				:std_logic_vector(3 downto 0) := "1001";
+	constant	CMD_CONF_READ		:std_logic_vector(3 downto 0) := "1010";
+	constant	CMD_CONF_WRITE	:std_logic_vector(3 downto 0) := "1011";
+	constant	CMD_MEM_READ_M	:std_logic_vector(3 downto 0) := "1100";
+	constant	CMD_DU_ADR_CYC	:std_logic_vector(3 downto 0) := "1101";
+	constant	CMD_MEN_READ_L	:std_logic_vector(3 downto 0) := "1110";
+	constant	CMD_MEM_WRITE_I	:std_logic_vector(3 downto 0) := "1111";
+
+	signal		MUX							:std_logic_vector(31 downto 0); 
+	signal		CONFIG_ADDR			:std_logic_vector( 7 downto 0); 
+
+begin
+
+	CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);
+
+--*******************************************************************
+--*********************** PCI Read Address **************************
+--*******************************************************************
+
+	process (CF_RD_COM, CONFIG_ADDR) 
+	begin
+
+		if	CF_RD_COM = '1'	then
+
+			if		CONFIG_ADDR = X"00"	then	READ_SEL <= "000";
+			elsif	CONFIG_ADDR = X"04"	then	READ_SEL <= "001";
+			elsif	CONFIG_ADDR = X"08"	then	READ_SEL <= "010";
+			elsif	CONFIG_ADDR = X"10"	then	READ_SEL <= "011";
+			elsif	CONFIG_ADDR = X"3C"	then	READ_SEL <= "100";
+			elsif	CONFIG_ADDR = X"40"	then	READ_SEL <= "101";
+			else								READ_SEL <= "111";
+			end if;
+		else									READ_SEL <= "111";
+		end if;
+	end process;
+
+end architecture CONFIG_RD_0_DESIGN;
+