X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/377c02420489dd18db3ce053a075d7eca4ae799b..d68161344eda14780ae6a88435c03e3cf24b47e0:/dhwk/source/config_3Ch.vhd

diff --git a/dhwk/source/config_3Ch.vhd b/dhwk/source/config_3Ch.vhd
index 642a484..1cc7f80 100644
--- a/dhwk/source/config_3Ch.vhd
+++ b/dhwk/source/config_3Ch.vhd
@@ -7,26 +7,26 @@ library IEEE;
 use IEEE.std_logic_1164.all;
 
 entity CONFIG_3CH is
-    port
-	(
-	PCI_CLOCK			:in		std_logic;
-	PCI_RSTn			:in		std_logic;
-	AD_REG				:in		std_logic_vector (31 downto 0);
-	CBE_REGn			:in		std_logic_vector ( 3 downto 0);
-	CONF_WR_3CH	 	:in		std_logic;
-	CONF_DATA_3CH	:out	std_logic_vector (31 downto 0)
-    );
+        port (
+                PCI_CLOCK	:in std_logic;
+                PCI_RSTn	:in std_logic;
+                AD_REG		:in std_logic_vector (31 downto 0);
+                CBE_REGn	:in std_logic_vector ( 3 downto 0);
+                CONF_WR_3CH	:in std_logic;
+                CONF_DATA_3CH	:out std_logic_vector (31 downto 0)
+        );
 end entity CONFIG_3CH;
 
 architecture CONFIG_3CH_DESIGN of CONFIG_3CH is
 
 -- PCI Configuration Space Header Addr : HEX 3C --
 
-	signal		CONF_MAX_LAT		:std_logic_vector (31 downto 24);
-	signal		CONF_MIN_GNT		:std_logic_vector (23 downto 16);  
-	signal		CONF_INT_PIN		:std_logic_vector (15 downto  8);
-	signal		CONF_INT_LINE		:std_logic_vector ( 7 downto  0);  
+	signal CONF_MAX_LAT :std_logic_vector (31 downto 24);
+	signal CONF_MIN_GNT :std_logic_vector (23 downto 16);  
+	signal CONF_INT_PIN :std_logic_vector (15 downto  8);
+	signal CONF_INT_LINE :std_logic_vector ( 7 downto  0);  
 
+	constant cmd_conf_write :std_logic_vector(3 downto 0) := "1011";
 begin 
 
 --*******************************************************************
@@ -42,25 +42,18 @@ begin
 --	CONF_INT_PIN	<= X"04";				-- Interrupt D
 --	CONF_INT_PIN	<= X"05 - FF0";	-- Reserviert
 
-	process (PCI_CLOCK,PCI_RSTn) 
-	begin
-		if PCI_RSTn = '0' then	CONF_INT_LINE <= (others =>'0');
-	
-		elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+process (PCI_CLOCK,PCI_RSTn) 
+begin
+        if PCI_RSTn = '0' then
+                CONF_INT_LINE <= (others => '0');
 
-			if			CONF_WR_3CH	 = '1'and CBE_REGn(0) = '0' then 
+        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then 
+                        CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
+                end if;
+        end if;
+end process;
 
-							CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
-				else 	CONF_INT_LINE(7 downto 0) <= CONF_INT_LINE(7 downto 0);
-			end if;
-
-		end if;
-
-	end process;
-
-	CONF_DATA_3CH	<= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE ;
+CONF_DATA_3CH	<= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;
 
 end architecture CONFIG_3CH_DESIGN;
-
-
-