X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/40a1f26c3a09dbd1f71f4fd7f3aca74f387a09db..7af9c8491ec2f4c8a5f6d9b3321d697b7b08b001:/ethernet/source/top.vhd?ds=sidebyside diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd index af81bdd..c031ae6 100644 --- a/ethernet/source/top.vhd +++ b/ethernet/source/top.vhd @@ -1,4 +1,7 @@ -entity top is +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +entity ethernet is PORT( PCI_AD : INOUT std_logic_vector(31 downto 0); PCI_CLOCK : IN std_logic; @@ -28,10 +31,12 @@ PORT( MCRS_PAD_I : IN std_logic; MD_PAD_IO : INOUT std_logic; MDC_PAD_O : OUT std_logic; + + LED_2 : OUT std_logic ); -end top; +end ethernet; -architecture bla of top is +architecture ethernet_arch of ethernet is COMPONENT eth_top PORT( @@ -69,6 +74,8 @@ PORT( mdc_pad_o : OUT std_logic; md_pad_o : OUT std_logic; md_padoe_o : OUT std_logic; + m_wb_cti_o : OUT std_logic_vector(2 downto 0); + m_wb_bte_o : OUT std_logic_vector(1 downto 0); int_o : OUT std_logic ); END COMPONENT; @@ -147,6 +154,21 @@ PORT( ); END COMPONENT; +component icon +port ( + control0 : out std_logic_vector(35 downto 0) + ); +end component; + +component ila +port ( + control : in std_logic_vector(35 downto 0); + clk : in std_logic; + data : in std_logic_vector(63 downto 0); + trig0 : in std_logic_vector(31 downto 0) + ); +end component; + signal pci_rst_o : std_logic; signal pci_rst_oe_o : std_logic; signal pci_inta_o : std_logic; @@ -169,57 +191,111 @@ signal pci_perr_o : std_logic; signal pci_perr_oe_o : std_logic; signal pci_serr_o : std_logic; signal pci_serr_oe_o : std_logic; -signal pci_ad_oe_o : std_logic; -signal pci_cbe_oe_o : std_logic; +signal pci_ad_oe_o : std_logic_vector(31 downto 0); +signal pci_cbe_oe_o : std_logic_vector(3 downto 0); signal pci_ad_o : std_logic_vector (31 downto 0); signal pci_cbe_o : std_logic_vector (3 downto 0); +signal wb_clk_i : std_logic; +signal wb_rst_i : std_logic; +signal wb_dat_i : std_logic_vector (31 downto 0); +signal wb_dat_o : std_logic_vector (31 downto 0); +signal wb_adr_i : std_logic_vector (11 downto 2); +signal wb_sel_i : std_logic_vector (3 downto 0); +signal wb_we_i : std_logic; +signal wb_cyc_i : std_logic; +signal wb_stb_i : std_logic; +signal wb_ack_o : std_logic; +signal wb_err_o : std_logic; +signal m_wb_adr_o : std_logic_vector(31 downto 0); +signal m_wb_sel_o : std_logic_vector(3 downto 0); +signal m_wb_we_o : std_logic; +signal m_wb_dat_o : std_logic_vector(31 downto 0); +signal m_wb_dat_i : std_logic_vector(31 downto 0); +signal m_wb_cyc_o : std_logic; +signal m_wb_stb_o : std_logic; +signal m_wb_ack_i : std_logic; +signal m_wb_err_i : std_logic; +signal md_pad_o : std_logic; +signal md_padoe_o : std_logic; +signal int_o : std_logic; +signal wbm_adr_o : std_logic_vector(31 downto 0); + +signal m_wb_cti_o : std_logic_vector(2 downto 0); +signal m_wb_bte_o : std_logic_vector(1 downto 0); + +signal control0 : std_logic_vector(35 downto 0); +signal data : std_logic_vector(63 downto 0); +signal trig0 : std_logic_vector(31 downto 0); + + BEGIN -PCI_RSTn <= if (pci_rst_oe_o = '1') then pci_rst_o else 'Z'; -PCI_INTAn <= if (pci_inta_oe_o = '1') then pci_inta_o else 'Z'; -PCI_REQn <= if (pci_req_oe_o = '1') then pci_req_o else 'Z'; -PCI_FRAMEn <= if (pci_frame_oe_o '1') then pci_frame_o else 'Z'; -PCI_IRDYn <= if (pci_irdy_oe_o = '1') then pci_irdy_o else 'Z'; -PCI_DEVSELn <= if (pci_devsel_oe_o = '1') then pci_devsel_o else 'Z'; -PCI_TRDYn <= if (pci_trdy_oe_o = '1') then pci_trdy_o else 'Z'; -PCI_STOPn <= if (pci_stop_oe_o = '1') then pci_stop_o else 'Z'; -PCI_AD <= if (pci_ad_oe_o = '1') then pci_ad_o else (others => 'Z'); -PCI_CBEn <= if (pci_cbe_oe_o = '1') then pci_cbe_o else (others => 'Z'); -PCI_PAR <= if (pci_par_oe_o = '1') then pci_par_o else 'Z'; -PCI_PERRn <= if (pci_perr_oe_o = '1') then pci_perr_o else 'Z'; -PCI_SERRn <= if (pci_serr_oe_o = '1') then pci_serr_o else 'Z'; +PCI_RSTn <= pci_rst_o when (pci_rst_oe_o = '1') else 'Z'; +PCI_INTAn <= pci_inta_o when (pci_inta_oe_o = '1') else 'Z'; +PCI_REQn <= pci_req_o when (pci_req_oe_o = '1') else 'Z'; +PCI_FRAMEn <= pci_frame_o when (pci_frame_oe_o = '1') else 'Z'; +PCI_IRDYn <= pci_irdy_o when (pci_irdy_oe_o = '1') else 'Z'; +PCI_DEVSELn <= pci_devsel_o when (pci_devsel_oe_o = '1') else 'Z'; +PCI_TRDYn <= pci_trdy_o when (pci_trdy_oe_o = '1') else 'Z'; +PCI_STOPn <= pci_stop_o when (pci_stop_oe_o = '1') else 'Z'; +PCI_PAR <= pci_par_o when (pci_par_oe_o = '1') else 'Z'; +PCI_PERRn <= pci_perr_o when (pci_perr_oe_o = '1') else 'Z'; +PCI_SERRn <= pci_serr_o when (pci_serr_oe_o = '1') else 'Z'; +MD_PAD_IO <= md_pad_o when (md_padoe_o = '1') else 'Z'; + +BLA1: FOR i in 31 downto 0 generate +PCI_AD(i) <= pci_ad_o(i) when (pci_ad_oe_o(i) = '1') else 'Z'; +end generate; + +BLA2: FOR i in 3 downto 0 generate +PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z'; +end generate; + +wb_adr_i(11 downto 8) <= (others => '0'); +wb_adr_i(7 downto 2) <= wbm_adr_o (7 downto 2); + +wb_clk_i <= PCI_CLOCK; + +data(31 downto 0) <= wbm_adr_o; +data(40 downto 33) <= wbm_adr_o (7 downto 0); +data(63 downto 41) <= (others => '0'); + +trig0(31 downto 0) <= ( + 0 => wb_stb_i, + others => '0' +); Inst_pci_bridge32: pci_bridge32 PORT MAP( - wb_clk_i => , - wb_rst_i => , - wb_rst_o => , - wb_int_i => , - wb_int_o => , - wbs_adr_i => , - wbs_dat_i => , - wbs_dat_o => , - wbs_sel_i => , - wbs_cyc_i => , - wbs_stb_i => , - wbs_we_i => , - wbs_cti_i => , - wbs_bte_i => , - wbs_ack_o => , - wbs_rty_o => , - wbs_err_o => , - wbm_adr_o => , - wbm_dat_i => , - wbm_dat_o => , - wbm_sel_o => , - wbm_cyc_o => , - wbm_stb_o => , - wbm_we_o => , - wbm_cti_o => , - wbm_bte_o => , - wbm_ack_i => , - wbm_rty_i => , - wbm_err_i => , + wb_clk_i => wb_clk_i , + wb_rst_i => '0', + wb_rst_o => wb_rst_i, + wb_int_i => int_o, + -- wb_int_o => , + wbs_adr_i => m_wb_adr_o , + wbs_dat_i => m_wb_dat_o, + wbs_dat_o => m_wb_dat_i, + wbs_sel_i => m_wb_sel_o, + wbs_cyc_i => m_wb_cyc_o, + wbs_stb_i => m_wb_stb_o, + wbs_we_i => m_wb_we_o, + wbs_cti_i => m_wb_cti_o, + wbs_bte_i => m_wb_bte_o, + wbs_ack_o => m_wb_ack_i, + -- wbs_rty_o => , + wbs_err_o => m_wb_err_i, + wbm_adr_o => wbm_adr_o, + wbm_dat_i => wb_dat_o, + wbm_dat_o => wb_dat_i, + wbm_sel_o => wb_sel_i, + wbm_cyc_o => wb_cyc_i, + wbm_stb_o => wb_stb_i, + wbm_we_o => wb_we_i, + -- wbm_cti_o => , + -- wbm_bte_o => , + wbm_ack_i => wb_ack_o , + wbm_rty_i => '0', + wbm_err_i => wb_err_o, pci_clk_i => PCI_CLOCK, pci_rst_i => PCI_RSTn, pci_rst_o => pci_rst_o , @@ -263,41 +339,56 @@ Inst_pci_bridge32: pci_bridge32 PORT MAP( ); Inst_eth_top: eth_top PORT MAP( - wb_clk_i => , - wb_rst_i => , - wb_dat_i => , - wb_dat_o => , - wb_adr_i => , - wb_sel_i => , - wb_we_i => , - wb_cyc_i => , - wb_stb_i => , - wb_ack_o => , - wb_err_o => , - m_wb_adr_o => , - m_wb_sel_o => , - m_wb_we_o => , - m_wb_dat_o => , - m_wb_dat_i => , - m_wb_cyc_o => , - m_wb_stb_o => , - m_wb_ack_i => , - m_wb_err_i => , - mtx_clk_pad_i => , - mtxd_pad_o => , - mtxen_pad_o => , - mtxerr_pad_o => , - mrx_clk_pad_i => , - mrxd_pad_i => , - mrxdv_pad_i => , - mrxerr_pad_i => , - mcoll_pad_i => , - mcrs_pad_i => , - mdc_pad_o => , - md_pad_i => , - md_pad_o => , - md_padoe_o => , - int_o => + wb_clk_i => wb_clk_i , + wb_rst_i => wb_rst_i , + wb_dat_i => wb_dat_i , + wb_dat_o => wb_dat_o , + wb_adr_i => wb_adr_i , + wb_sel_i => wb_sel_i , + wb_we_i => wb_we_i , + wb_cyc_i => wb_cyc_i , + wb_stb_i => wb_stb_i, + wb_ack_o => wb_ack_o , + wb_err_o => wb_err_o , + m_wb_adr_o => m_wb_adr_o, + m_wb_sel_o => m_wb_sel_o, + m_wb_we_o => m_wb_we_o , + m_wb_dat_o => m_wb_dat_o, + m_wb_dat_i => m_wb_dat_i, + m_wb_cyc_o => m_wb_cyc_o, + m_wb_stb_o => m_wb_stb_o, + m_wb_ack_i => m_wb_ack_i, + m_wb_err_i => m_wb_err_i, + mtx_clk_pad_i => MTX_CLK_PAD_I, + mtxd_pad_o => MTXD_PAD_O, + mtxen_pad_o => MTXEN_PAD_O, + mtxerr_pad_o => LED_2, + mrx_clk_pad_i => MRX_CLK_PAD_I, + mrxd_pad_i => MRXD_PAD_I, + mrxdv_pad_i => MRXDV_PAD_I, + mrxerr_pad_i => MRXERR_PAD_I, + mcoll_pad_i => MCOLL_PAD_I, + mcrs_pad_i => MCRS_PAD_I, + mdc_pad_o => MDC_PAD_O, + md_pad_i => MD_PAD_IO, + md_pad_o => md_pad_o, + md_padoe_o => md_padoe_o, + m_wb_cti_o => m_wb_cti_o, + m_wb_bte_o => m_wb_bte_o, + int_o => int_o ); -end architecture bla; +i_icon : icon +port map ( + control0 => control0 + ); + +i_ila : ila +port map ( + control => control0, + clk => PCI_CLOCK, + data => data, + trig0 => trig0 + ); + +end architecture ethernet_arch;