X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/696ded12bcd3df47aeefae2c685029a799d84abd..2612d712ff5ef3f17a3d55ae22c71a1913fa1fee:/dhwk/source/config_04h.vhd diff --git a/dhwk/source/config_04h.vhd b/dhwk/source/config_04h.vhd index 906a9ca..70d0c9f 100644 --- a/dhwk/source/config_04h.vhd +++ b/dhwk/source/config_04h.vhd @@ -7,109 +7,107 @@ library IEEE; use IEEE.std_logic_1164.all; entity CONFIG_04H is - port - ( - PCI_CLOCK :in std_logic; - PCI_RSTn :in std_logic; - SERR :in std_logic; - PERR :in std_logic; - AD_REG :in std_logic_vector(31 downto 0); - CBE_REGn :in std_logic_vector( 3 downto 0); - CONF_WR_04H :in std_logic; - CONF_DATA_04H :out std_logic_vector(31 downto 0) - ); + port + ( + PCI_CLOCK :in std_logic; + PCI_RSTn :in std_logic; + SERR :in std_logic; + PERR :in std_logic; + AD_REG :in std_logic_vector(31 downto 0); + CBE_REGn :in std_logic_vector( 3 downto 0); + CONF_WR_04H :in std_logic; + CONF_DATA_04H :out std_logic_vector(31 downto 0) + ); end entity CONFIG_04H; architecture CONFIG_04H_DESIGN of CONFIG_04H is - signal CONF_STATUS :std_logic_vector(31 downto 16); - signal CONF_COMMAND :std_logic_vector(15 downto 0); - + signal CONF_STATUS :std_logic_vector(31 downto 16); + signal CONF_COMMAND :std_logic_vector(15 downto 0); begin ---******************************************************************* ---************* PCI Configuration Space Header "STATUS" ************* ---******************************************************************* - - CONF_STATUS(20 downto 16) <= "00000" ;-- Reserved - CONF_STATUS(21 ) <= '0' ;-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz - CONF_STATUS(22 ) <= '0' ;-- MAS/TAR: "R_O" - CONF_STATUS(23 ) <= '0' ;-- ???/???: "R_O" : fast back-to-back - CONF_STATUS(24 ) <= '0' ;-- Master : ---CONF_STATUS(26 downto 25) <= "00" ;-- Mas/Tar: "R_O" : timing fast for "DEVSEL" - CONF_STATUS(26 downto 25) <= "01" ;-- Mas/Tar: "R_O" : timing medium for "DEVSEL" ---CONF_STATUS(26 downto 25) <= "10" ;-- Mas/Tar: "R_O" : timing slow for "DEVSEL" ---CONF_STATUS(26 downto 25) <= "11" ;-- Mas/Tar: "R_O" : reserved - CONF_STATUS(27 ) <= '0' ;-- Target : "R_W" : Taget-Abort - CONF_STATUS(28 ) <= '0' ;-- Master : "R_W" : Taget-Abort - CONF_STATUS(29 ) <= '0' ;-- Master : "R_W" : Master-Abort ---CONF_STATUS(30 ) <= SERR ;-- Mas/Tar: "R_W" : SERR ---CONF_STATUS(31 ) <= PERR ;-- Mas/Tar: "R_W" : PERR - - process (PCI_CLOCK,PCI_RSTn) - begin - if PCI_RSTn = '0' then CONF_STATUS(30) <= '0'; - CONF_STATUS(31) <= '0'; - - elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then - - if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then - - CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30)); - CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31)); - - else CONF_STATUS(30) <= SERR or CONF_STATUS(30); - CONF_STATUS(31) <= PERR or CONF_STATUS(31); - - end if; - end if; - end process; - ---******************************************************************* ---*********** PCI Configuration Space Header "COMMAND" ************** ---******************************************************************* - --- CONF_COMMAND( 0) <= '0';-- I/O Space accesses ??? --- CONF_COMMAND( 1) <= '0';-- Mem Space accesses ??? --- CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus --- CONF_COMMAND( 3) <= '0';-- Special Cycle ??? --- CONF_COMMAND( 4) <= '0';-- Master ??? --- CONF_COMMAND( 5) <= '0';-- VGA ??? --- CONF_COMMAND( 6) <= '0';-- Party checking enable/disable - CONF_COMMAND( 7) <= '0';-- address/data stepping ??? --- CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn" --- CONF_COMMAND( 9) <= '0';-- fast back-to-back --- CONF_COMMAND(10) <= '0';-- Reserved --- CONF_COMMAND(11) <= '0';-- Reserved --- CONF_COMMAND(12) <= '0';-- Reserved --- CONF_COMMAND(13) <= '0';-- Reserved --- CONF_COMMAND(14) <= '0';-- Reserved --- CONF_COMMAND(15) <= '0';-- Reserved - - process (PCI_CLOCK,PCI_RSTn) - begin - if PCI_RSTn = '0' then CONF_COMMAND(15 downto 8) <= (others =>'0'); - CONF_COMMAND( 6 downto 0) <= (others =>'0'); - - elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then - - if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then - - CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8); - else CONF_COMMAND(15 downto 8) <= CONF_COMMAND(15 downto 8); - end if; - - - if CONF_WR_04H = '1'and CBE_REGn(0) = '0' then - - CONF_COMMAND( 6 downto 0) <= AD_REG( 6 downto 0); - else CONF_COMMAND( 6 downto 0) <= CONF_COMMAND( 6 downto 0); - end if; - - end if; - end process; - - CONF_DATA_04H <= CONF_STATUS & CONF_COMMAND; + --******************************************************************* + --************* PCI Configuration Space Header "STATUS" ************* + --******************************************************************* + + CONF_STATUS(20 downto 16) <= "00000";-- Reserved + CONF_STATUS(21 ) <= '0';-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz + CONF_STATUS(22 ) <= '0';-- MAS/TAR: "R_O" + CONF_STATUS(23 ) <= '0';-- ???/???: "R_O" : fast back-to-back + CONF_STATUS(24 ) <= '0';-- Master : + --CONF_STATUS(26 downto 25) <= "00";-- Mas/Tar: "R_O" : timing fast for "DEVSEL" + CONF_STATUS(26 downto 25) <= "01";-- Mas/Tar: "R_O" : timing medium for "DEVSEL" + --CONF_STATUS(26 downto 25) <= "10";-- Mas/Tar: "R_O" : timing slow for "DEVSEL" + --CONF_STATUS(26 downto 25) <= "11";-- Mas/Tar: "R_O" : reserved + CONF_STATUS(27 ) <= '0';-- Target : "R_W" : Taget-Abort + CONF_STATUS(28 ) <= '0';-- Master : "R_W" : Taget-Abort + CONF_STATUS(29 ) <= '0';-- Master : "R_W" : Master-Abort + --CONF_STATUS(30 ) <= SERR;-- Mas/Tar: "R_W" : SERR + --CONF_STATUS(31 ) <= PERR;-- Mas/Tar: "R_W" : PERR + + process (PCI_CLOCK,PCI_RSTn) + begin + if PCI_RSTn = '0' then + CONF_STATUS(30) <= '0'; + CONF_STATUS(31) <= '0'; + + elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then + if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then + CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30)); + CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31)); + + else + CONF_STATUS(30) <= SERR or CONF_STATUS(30); + CONF_STATUS(31) <= PERR or CONF_STATUS(31); + + end if; + end if; +end process; + + --******************************************************************* + --*********** PCI Configuration Space Header "COMMAND" ************** + --******************************************************************* + +-- CONF_COMMAND( 0) <= '0';-- I/O Space accesses ??? +-- CONF_COMMAND( 1) <= '0';-- Mem Space accesses ??? +-- CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus +-- CONF_COMMAND( 3) <= '0';-- Special Cycle ??? +-- CONF_COMMAND( 4) <= '0';-- Master ??? +-- CONF_COMMAND( 5) <= '0';-- VGA ??? +-- CONF_COMMAND( 6) <= '0';-- Party checking enable/disable +CONF_COMMAND( 7) <= '0';-- address/data stepping ??? +-- CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn" +-- CONF_COMMAND( 9) <= '0';-- fast back-to-back +-- CONF_COMMAND(10) <= '0';-- Reserved +-- CONF_COMMAND(11) <= '0';-- Reserved +-- CONF_COMMAND(12) <= '0';-- Reserved +-- CONF_COMMAND(13) <= '0';-- Reserved +-- CONF_COMMAND(14) <= '0';-- Reserved +-- CONF_COMMAND(15) <= '0';-- Reserved + +process (PCI_CLOCK,PCI_RSTn) +begin + if PCI_RSTn = '0' then + CONF_COMMAND(15 downto 8) <= (others =>'0'); + CONF_COMMAND( 6 downto 0) <= (others =>'0'); + + elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then + + if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then + CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8); + else + CONF_COMMAND(15 downto 8) <= CONF_COMMAND(15 downto 8); + end if; + + if CONF_WR_04H = '1'and CBE_REGn(0) = '0' then + CONF_COMMAND( 6 downto 0) <= AD_REG( 6 downto 0); + else + CONF_COMMAND( 6 downto 0) <= CONF_COMMAND( 6 downto 0); + end if; + end if; +end process; + +CONF_DATA_04H <= CONF_STATUS & CONF_COMMAND; end architecture CONFIG_04H_DESIGN;